CY7C64013
CY7C64113
.
Logic Block Diagram
6-MHz crystal
PLL
48 MHz
Clock
Divider
12 MHz
PROM
8 KB
8-bit Bus
Interrupt
Controller
12-MHz
8-bit
CPU
USB
SIE
USB
Transceiver
D+[0] Upstream
D–[0] USB Port
RAM
256 byte
GPIO
PORT 0
P0[7:0]
6 MHz
12-bit
Timer
GPIO
PORT 1
P1[2:0]
P1[7:3]
CY7C64113 only
Watch Dog
Timer
GPIO/
HAPI
PORT 2
P2[0,1,7]
P2[2]; Latch_Empty
P2[3]; Data_Ready
P2[4]; STB
P2[5]; OE
P2[6]; CS
Power-On
Reset
P3[2:0]
GPIO
PORT 3
P3[7:3]
High Current
Outputs
Additional
High Current
Outputs
DAC
PORT
DAC[0]
DAC[2]
DAC[7]
CY7C64113 only
I
2
C
Interface
SCLK
SDATA
*I
2
C compatible interface enabled by firmware through
P2[1:0] or P1[1:0]
Document #: 38-08001 Rev. **
Page 7 of 48
CYPRESS [ CYPRESS SEMICONDUCTOR ]
