CY8C24x23A Final Data Sheet
3. Electrical Specifications
Table 3-26. 2.7V AC Operational Amplifier Specifications
Symbol
T
ROA
Description
Rising Settling Time from 80% of
∆
V to 0.1% of
∆
V (10 pF
load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
T
SOA
Falling Settling Time from 20% of
∆
V to 0.1% of
∆
V (10 pF
load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
SR
ROA
Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
SR
FOA
Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
BW
OA
Gain Bandwidth Product
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
E
NOA
Noise at 1 kHz (Power = Medium, Opamp Bias = High)
0.67
2.8
–
–
–
100
–
–
–
MHz
MHz
nV/rt-Hz
0.24
1.8
–
–
–
–
V/
µ
s
V/
µ
s
0.31
2.7
–
–
–
–
V/
µ
s
V/
µ
s
–
–
–
–
5.41
0.72
µ
s
µ
s
Min
Typ
Max
Units
Notes
–
–
–
–
3.92
0.72
µ
s
µ
s
3.4.4
AC Digital Block Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C
≤
T
A
≤
85°C, 3.0V to 3.6V and -40°C
≤
T
A
≤
85°C, or 2.4V to 3.0V and -40°C
≤
T
A
≤
85°C, respectively. Typical parameters
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
Table 3-27. 5V and 3.3V AC Digital Block Specifications
Function
Timer
Capture Pulse Width
Maximum Frequency, No Capture
Maximum Frequency, With Capture
Counter
Enable Pulse Width
Maximum Frequency, No Enable Input
Maximum Frequency, Enable Input
Dead Band
Kill Pulse Width:
Asynchronous Restart Mode
Synchronous Restart Mode
Disable Mode
Maximum Frequency
CRCPRS
Maximum Input Clock Frequency
(PRS Mode)
CRCPRS
Maximum Input Clock Frequency
(CRC Mode)
SPIM
SPIS
Maximum Input Clock Frequency
Maximum Input Clock Frequency
Width of SS_ Negated Between Transmissions
Transmitter
Receiver
Maximum Input Clock Frequency
Maximum Input Clock Frequency
20
50
a
50
a
–
–
–
–
–
50
–
–
a
Description
Min
50
a
–
–
50
a
–
–
–
–
–
–
–
–
Typ
–
Max
Units
ns
MHz
MHz
ns
MHz
MHz
Notes
49.2
24.6
–
49.2
24.6
4.75V < Vdd < 5.25V.
4.75V < Vdd < 5.25V.
–
–
–
–
–
–
–
–
–
–
–
–
–
–
49.2
49.2
24.6
8.2
4.1
–
24.6
24.6
ns
ns
ns
MHz
MHz
MHz
MHz
ns
ns
MHz
MHz
Maximum data rate
at 3.08 MHz due to 8 x over
Maximum data rate at 4.1 MHz due to 2 x over
clocking.
4.75V < Vdd < 5.25V.
4.75V < Vdd < 5.25V.
clocking.
Maximum data rate
at 3.08 MHz due to 8 x over
clocking.
a. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
September 8, 2004
Document No. 38-12028 Rev. *B
34
CYPRESS [ CYPRESS SEMICONDUCTOR ]
