DS1007
LOGIC DIAGRAM
Figure 1
PART NUMBER DELAY TABLE (t
PLH
)
Table 1
PART #
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
DS1007-1
3ns
4ns
5ns
6ns
9ns
13ns
18ns
DS1007-2
4
6
8
10
12
14
16
DS1007-3
3
3
3
3
10
10
10
DS1007-4
4
4
4
4
12
12
12
DS1007-5
5
5
5
5
15
15
15
DS1007-6
6
6
6
6
20
20
20
DS1007-7
7
7
7
7
25
25
25
DS1007-8
8
8
8
8
30
30
30
DS1007-9
9
9
9
9
35
35
35
DS1007-10
10
10
10
10
40
40
40
DS1007-11
3
4
6
8
10
12
14
DS1007-12
3
4
6
8
10
15
20
DS1007-13
3
4
6
8
12
15
20
DS1007-14
7
7
7
7
9
9
9
Custom delays available. Out 1 through Out 4 can be custom set from 3 to 10 ns (leading edge only
accuracy). Out 5 through Out 7 can be set from 9 to 40 ns (both leading and trailing edge accuracy).
2 of 6
DALLAS [ DALLAS SEMICONDUCTOR ]
