DS1643
DS1643
Nonvolatile Timekeeping RAM
FEATURES
PIN ASSIGNMENT
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
CE2
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
•
Form, fit, and function compatible with the MK48T08
Timekeeping RAM
•
Integrated NV SRAM, real time clock, crystal, power–
fail control circuit and lithium energy source
•
Standard JEDEC bytewide 8K x 8 static RAM pinout
•
Clock
registers are accessed identical to the static
RAM. These registers are resident in the eight top
RAM locations.
the absence of power
•
Totally nonvolatile with over 10 years of operation in
•
Access times of 120 ns and 150 ns
•
Quartz accuracy
±1
minute a month @ 25°C, factory
calibrated
•
BCD coded year, month, date, day, hours, minutes,
and seconds with leap year compensation valid up to
2100
28–PIN ENCAPSULATED PACKAGE
(700 MIL EXTENDED)
•
Power–fail
write protection allows for
±10%
V
CC
power supply tolerance
ORDERING INFORMATION
DS1643–XXX
28–pin DIP module
–120 120 ns access
–150 150 ns access
DESCRIPTION
The DS1643 is an 8K x 8 nonvolatile static RAM with a
full function real time clock which are both accessible in
a bytewide format. The nonvolatile time keeping RAM is
pin and function equivalent to any JEDEC standard
8K x 8 SRAM. The device can also be easily substituted
in ROM, EPROM and EEPROM sockets providing read/
write nonvolatility and the addition of the real time clock
function. The real time clock information resides in the
eight uppermost RAM locations. The RTC registers
contain year, month, date, day, hours, minutes, and se-
conds data in 24 hour BCD format. Corrections for the
day of the month and leap year are made automatically.
The RTC clock registers are double buffered to avoid
access of incorrect data that can occur during clock up-
date cycles. The double buffered system also prevents
time loss as the timekeeping countdown continues un-
abated by access to time register data. The DS1643
also contains its own power–fail circuitry which dese-
lects the device when the V
CC
supply is in an out of toler-
ance condition. This feature prevents loss of data from
unpredictable system operation brought on by low V
CC
as errant access and update cycles are avoided.
ECopyright
1995 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor data books.
041697 1/11
DALLAS [ DALLAS SEMICONDUCTOR ]
