D8259
Programmable Interrupt Controller
ver 1.04
● Writing and reading of interrupt mask reg-
O V E R V I E W
ister (IMR) through data bus
The D8259 is a soft Core of Programma-
ble Interrupt Controller. It is fully compatible
with the 82C59A device. The D8259 Core
manages up to 8-vectored priority interrupts
for processor. Programming it to cascade
allows for up to 64 vectored interrupts. More
than 64 vectored interrupts can be accom-
plished by programming to Poll Command
Mode.
K E Y F E A T U R E S
● 8 vectored priority interrupts
● Up to sixty-four vectored priority interrupts
with cascading
● Support for all 82C59A modes features
○
MCS-80/85 and 8088/8086 processor
modes
D8259 can operate in all 82C59A modes,
and supports all 82C59A features:
○
Fully nested mode and special fully nested
mode
● MCS-80/85 and 8088/8086 processor
modes
○
○
○
○
Special mask mode
Buffered mode
● Fully nested mode and special fully
nested mode
Pool command mode
● Special mask mode
● Buffered mode
Cascade mode with master or slave selec-
tion
● Pool command mode
○
○
Automatic end-of-interrupt mode
● Cascade mode with master or slave se-
Specific and non-specific end-of-interrupt
commands
lection
● Automatic end-of-interrupt mode
○
○
Automatic and Specific Rotation
● Specific and non-specific end-of-interrupt
Edge and level triggered interrupt input
modes
commands
○
Reading of interrupt request register (IIR)
and in-service register (ISR) through data
bus
● Automatic and Specific Rotation
● Edge and level triggered interrupt input
modes
● Fully synthesizable, static design with no
● Reading of interrupt request register (IIR)
and in-service register (ISR) through data
bus.
internal tri-states
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