DFPMUL
Floating Point Pipelined Multiplier Unit
ver 2.70
OVERVIEW
The DFPMUL uses the
pipelined
mathemat-
ics algorithm to multiply two arguments. The
input numbers format is according to IEEE-
754 standard. DFPMUL supports single pre-
cision real number. Multiply operation was
pipelined up to 7 levels. Input data are fed
every clock cycle. The first result appears
after latency depending on pipeline level and
next results are available
each clock
cycle.
Full IEEE-754 precision and accuracy were
included.
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Fully synthesizable, static synchronous
design with no internal tri-states
DELIVERABLES
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Source code:
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VHDL Source Code or/and
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VERILOG Source Code or/and
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ALTERA’s Megafunction or/and
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EDIF netlist
VHDL & VERILOG test bench environ-
ment
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Active-HDL automatic simulation mac-
ros
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NCSim automatic simulation macros
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ModelSim automatic simulation macros
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Tests with reference responses
Technical documentation
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Installation notes
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HDL core specification
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Datasheet
Synthesis scripts
Example application
Technical support
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IP Core implementation support
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3 months maintenance
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APPLICATION
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Math coprocessors
DSP algorithms
Embedded arithmetic coprocessor
Data processing & control
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KEY FEATURES
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Full IEEE-754 compliance
Single precision real format support
Simple interface
No programming required
7 levels pipeline
Full accuracy and precision
Overflow, underflow and invalid operation
flags
Results available at every clock
Fully configurable
Delivery the IP Core updates, minor
and major versions changes
Delivery the documentation updates
Phone & email support
LICENSING
Comprehensible and clearly defined licensing
methods without royalty fees make using of
IP Core easy and simply.
Single Design
license allows using IP Core in
single FPGA bitstream and ASIC implemen-
http://www.DigitalCoreDesign.com
http://www.dcd.pl
All trademarks mentioned in this document
are trademarks of their respective owners.
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
DCD [ DIGITAL CORE DESIGN ]
