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DI2CS 参数 Datasheet PDF下载

DI2CS图片预览
型号: DI2CS
PDF下载: 下载PDF文件 查看货源
内容描述: I2C总线接口 - 从 [I2C Bus Interface - Slave]
分类和应用:
文件页数/大小: 4 页 / 148 K
品牌: DCD [ DIGITAL CORE DESIGN ]
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DI2CS  
I2C Bus Interface - Slave  
ver 3.02  
Fully synthesizable  
O V E R V I E W  
I2C is a two-wire, bi-directional serial bus that  
provides a simple and efficient method of  
data transmission over a short distance be-  
tween many devices. The DI2CS core pro-  
vides an interface between a microprocessor  
/microcontroller and an I2C bus. It can works  
as a slave transmitter or slave receiver de-  
pending on working mode determined by a  
master device. The DI2CS core incorporates  
all features required by the latest I2C specifi-  
cation including clock synchronization, arbi-  
tration and High-speed transmission mode.  
The DI2CS supports all the transmission  
speed modes.  
Static synchronous design with positive  
edge clocking and synchronous reset  
No internal tri-states  
Scan test ready  
A P P L I C A T I O N S  
Embedded microprocessor boards  
Consumer and professional audio/video  
Home and automotive radio  
Low-power applications  
Communication systems  
Cost-effective reliable automotive sys-  
K E Y F E A T U R E S  
tems  
Conforms to v.2.1 of the I2C specification  
D E L I V E R A B L E S  
Source code:  
VHDL Source Code or/and  
VERILOG Source Code or/and  
Encrypted, or plain text EDIF netlist  
VHDL & VERILOG test bench environ-  
ment  
Active-HDL automatic simulation mac-  
ros  
ModelSim automatic simulation macros  
Tests with reference responses  
Technical documentation  
Installation notes  
Slave operation  
Slave transmitter  
Slave receiver  
Supports 3 transmission speed modes  
Standard (up to 100 kb/s)  
Fast (up to 400 kb/s)  
High Speed (up to 3,4 Mb/s)  
Allows operation from a wide range of  
input clock frequencies  
Simple interface allows easy connection  
HDL core specification  
Datasheet  
to microprocessor/microcontroller devices  
Synthesis scripts  
Example application  
Technical support  
Interrupt generation  
User-defined data setup time  
All trademarks mentioned in this document  
are trademarks of their respective owners.  
http://www.DigitalCoreDesign.com  
http://www.dcd.pl  
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.