DP8051XP
Pipelined High Performance
8-bit Microcontroller
ver 3.10
O V E R V I E W
C P U F E A T U R E S
DP8051XP is a ultra high performance,
speed optimized soft core of a single-chip 8-
bit embedded controller dedicated for opera-
tion with fast (typically on-chip) and slow (off-
chip) memories. The core has been designed
with a special concern about performance to
power consumption ratio. This ratio is ex-
tended by an advanced power management
unit PMU.
● 100% software compatible with industry
standard 8051
● Pipelined RISC architecture enables to
execute instructions 10 times faster com-
pared to standard 8051
● 24 times faster multiplication
● 12 times faster addition
● 2 Data Pointers (DPTR) for faster memory
DP8051XP soft core is 100% binary-
compatible with the industry standard 8051 8-
bit microcontroller. There are two configura-
tions of DP8051XP: Harward where internal
data and program buses are separated, and
von Neumann with common program and ex-
ternal data bus. DP8051XP has Pipelined
RISC architecture 10 times faster compared
to standard architecture and executes 85-200
million instructions per second. This per-
formance can also be exploited to great advan-
tage in low power applications where the core
can be clocked over ten times more slowly
than the original implementation for no per-
formance penalty.
blocks copying
○
○
Advanced INC & DEC modes
Auto-switch of current DPTR
● Up to 256 bytes of internal (on-chip) Data
Memory
● Up to 64K bytes of internal (on-chip) or
external (off-chip) Program Memory
● Up to 16M bytes of external (off-chip) Data
Memory
● User programmable Program Memory Wait
States solution for wide range of memories
speed
● User programmable External Data Memory
Wait States solution for wide range of
memories speed
DP8051XP is fully customizable, which
means it is delivered in the exact configuration
to meet users’ requirements. There is no need
to pay extra for not used features and wasted
silicon. It includes fully automated testbench
with complete set of tests allowing easy
package validation at each stage of SoC de-
sign flow.
● De-multiplexed Address/Data bus to allow
easy connection to memory
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved.
DCD [ DIGITAL CORE DESIGN ]
