DP80C51
Pipelined High Performance
8-bit Microcontroller
ver 4.01
O V E R V I E W
C P U F E A T U R E S
DP80C51 is an ultra high performance,
speed optimized soft core of a single-chip 8-
bit embedded controller dedicated for opera-
tion with fast (typically on-chip) and slow (off-
chip) memories. The core has been designed
with a special concern for performance to
power consumption ratio. This ratio is ex-
tended by an advanced power management
unit PMU.
DP80C51 soft core is 100% binary and
pin compatible with the industry standard
8051 8-bit microcontroller. There are two con-
figurations of the DP80C51: Harward, where
external data and program buses are sepa-
rated, and von Neumann, with common pro-
gram and external data bus. DP80C51 has
Pipelined RISC architecture up to 10 times
faster compared to standard architecture and
executes 85-200 million instructions per
second. This performance can also be ex-
ploited to great advantage in low power appli-
cations where the core can be clocked over ten
times more slower than the original implemen-
tation for no performance penalty.
● 100% pin compatible with industry standard
8051
● 100% software compatible with industry
standard 8051
● Pipelined RISC architecture enables to
execute instructions up to 10 times faster
compared to standard 8051
● 24 times faster multiplication
● 12 times faster addition
● Up to 256 bytes of internal (on-chip) Data
Memory
● Up to 64K bytes of internal (on-chip) or
external (off-chip) Program Memory
● Up to 64K bytes of external (off-chip) Data
Memory
● User programmable Program Memory Wait
States solution for wide range of memories
speed
● User programmable External Data Memory
Wait States solution for wide range of
memories speed
DP80C51 is delivered with fully auto-
mated testbench and complete set of tests
allowing easy package validation at each stage
of SoC design flow.
● Dedicated signal for Program Memory
writes.
● Interface for additional Special Function
Registers
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