欢迎访问ic37.com |
会员登录 免费注册
发布采购

DR8051 参数 Datasheet PDF下载

DR8051图片预览
型号: DR8051
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能8位微控制器版本3.10 [High Performance 8-bit Microcontroller ver 3.10]
分类和应用: 微控制器
文件页数/大小: 8 页 / 112 K
品牌: DCD [ DIGITAL CORE DESIGN ]
 浏览型号DR8051的Datasheet PDF文件第2页浏览型号DR8051的Datasheet PDF文件第3页浏览型号DR8051的Datasheet PDF文件第4页浏览型号DR8051的Datasheet PDF文件第5页浏览型号DR8051的Datasheet PDF文件第6页浏览型号DR8051的Datasheet PDF文件第7页浏览型号DR8051的Datasheet PDF文件第8页  
DR8051  
High Performance  
8-bit Microcontroller  
ver 3.10  
O V E R V I E W  
C P U F E A T U R E S  
DR8051 is a high performance, area op-  
timized soft core of a single-chip 8-bit embed-  
ded controller dedicated for operation with fast  
(typically on-chip) and slow (off-chip) memo-  
ries. The core has been designed with a spe-  
cial concern about low power consumption.  
Additionally an advanced power management  
unit makes DR8051 core perfect for portable  
equipment where low power consumption is  
mandatory.  
100% software compatible with industry  
standard 8051  
RISC architecture enables to execute in-  
structions 6.7 times faster compared to  
standard 8051  
12 times faster multiplication  
9.6 times faster division  
Up to 256 bytes of internal (on-chip) Data  
Memory  
DR8051 soft core is 100% binary-  
compatible with the industry standard 8051 8-  
bit microcontroller. There are two configura-  
tions of DR8051: Harward where external data  
and program buses are separated, and von  
Neumann with common program and external  
data bus. DR8051 has RISC architecture 6.7  
times faster compared to standard architec-  
ture and executes 65-200 million instructions  
per second. This performance can also be ex-  
ploited to great advantage in low power appli-  
cations where the core can be clocked up to  
seven times more slowly than the original im-  
plementation for no performance penalty.  
DR8051 is delivered with fully automated  
testbench and complete set of tests allowing  
easy package validation at each stage of SoC  
design flow.  
Up to 64K bytes of Program Memory  
Up to 16M bytes of external (off-chip) Data  
Memory  
User programmable Program Memory Wait  
States solution for wide range of memories  
speed  
User programmable External Data Memory  
Wait States solution for wide range of  
memories speed  
De-multiplexed Address/Data bus to allow  
easy connection to memory  
Interface for additional Special Function  
Registers  
Fully synthesizable, static synchronous de-  
sign with positive edge clocking and no in-  
ternal tri-states  
All trademarks mentioned in this document  
are trademarks of their respective owners.  
http://www.DigitalCoreDesign.com  
http://www.dcd.pl  
Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved.