DSPI_FIFO
Serial Peripheral Interface
Master/Slave with FIFO
ver 1.07
to support interprocessor communications. A
O V E R V I E W
write-collision detector indicates when an at-
tempt is made to write data to the serial shift
register while a transfer is in progress. A mul-
tiple-master mode-fault detector automatically
disables DSPI_FIFO output drivers if more
than one SPI devices simultaneously attempts
to become bus master.
The DSPI_FIFO is a fully configurable SPI
master/slave device, which allows user to
configure polarity and phase of serial clock
signal SCK.
The DSPI_FIFO allows the microcontroller
to communicate with serial peripheral devices.
It is also capable of interprocessor communi-
cations in a multi-master system. A serial
clock line (SCK) synchronizes shifting and
sampling of the information on the two inde-
pendent serial data lines. DSPI_FIFO data are
simultaneously transmitted and received.
The DSPI_FIFO is a technology independ-
ent design that can be implemented in a vari-
ety of process technologies.
The DSPI_FIFO supports two DMA
modes: single transfer and multi-transfer.
These modes allow DSPI_FIFO to inter-
face to higher performance DMA units,
which can interleave their transfers be-
tween CPU cycles or execute multiple
byte transfers.
DSPI_FIFO is fully customizable, which
means it is delivered in the exact configuration
to meet users’ requirements. There is no need
to pay extra for not used features and wasted
silicon. It includes fully automated testbench
with complete set of tests allowing easy
package validation at each stage of SoC de-
sign flow.
The DSPI_FIFO system is flexible enough
to interface directly with numerous standard
product peripherals from several manufactur-
ers. The system can be configured as a mas-
ter or a slave device. Data rates as high as
CLK/8. Clock control logic allows a selection
of clock polarity and a choice of two funda-
mentally different clocking protocols to ac-
commodate most available synchronous serial
peripheral devices. When the SPI is config-
ured as a master, software selects one of
eight different bit rates for the serial clock.
The DSPI_FIFO automatically drive se-
lected by SSCR (Slave Select Control Regis-
ter) slave select outputs (SS7O – SS0O), and
address SPI slave device to exchange serially
shifted data. Error-detection logic is included
A P P L I C A T I O N S
● Embedded microprocessor boards
● Consumer and professional audio/video
● Home and automotive radio
● Digital multimeters
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http://www.dcd.pl
are trademarks of their respective owners.
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
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