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DSPIS 参数 Datasheet PDF下载

DSPIS图片预览
型号: DSPIS
PDF下载: 下载PDF文件 查看货源
内容描述: 串行外设接口 - 从 [Serial Peripheral Interface - Slave]
分类和应用:
文件页数/大小: 5 页 / 144 K
品牌: DCD [ DIGITAL CORE DESIGN ]
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DSPIS  
Serial Peripheral Interface –Slave  
ver 1.01  
master. Transmission is ended when the SS  
line goes high.  
O V E R V I E W  
The DSPIS is a fully configurable SPI ma  
slave device, designated to operate with pas-  
sive devices like memories, LCD drivers etc.  
The DSPIS allows user to configure polarity  
and phase of serial clock signal SCK.  
A serial clock line (SCK) synchronizes shift-  
ing and sampling of the information on the two  
independent serial data lines. DSPIS data are  
simultaneously transmitted and received.  
The DSPIS is a technology independent  
design that can be implemented in a variety of  
process technologies.  
DSPIS is fully customizable, which means  
it is delivered in the exact configuration to  
meet users’ requirements. There is no need to  
pay extra for not used features and wasted  
silicon. It includes fully automated testbench  
with complete set of tests allowing easy  
package validation at each stage of SoC de-  
sign flow.  
The DSPIS system is flexible enough to in-  
terface directly with numerous standard prod-  
uct peripherals from several manufacturers.  
Data rates as high as CLK/4. Clock control  
logic allows a selection of clock polarity and a  
choice of two fundamentally different clocking  
protocols to accommodate most available  
synchronous serial peripheral devices.  
The DSPIS allows the SPI Master to com-  
municate with passive devices. When trans-  
mission starts (SS Line goes low) the first por-  
tion of data is copied to the address register  
and then to the ADDRESS bus output, after  
transmission of the address the DSPIS gener-  
ates the read signal (RD) and copy DATAI bus  
contents to the transmitter shift register, and  
prepare data to be exchanged with SPI Mas-  
ter. During the next data portion transmission  
DSPIS simultaneously transmits data out and  
in. When the first data portion is received the  
DSPIS asserts DATAO bus generates the  
write signal (WE), then increments ADDRESS  
bus performs a read operation and prepare  
another data portion to be exchanged with SPI  
A P P L I C A T I O N S  
Embedded microprocessor boards  
Consumer and professional audio/video  
Home and automotive radio  
Digital multimeters  
All trademarks mentioned in this document  
are trademarks of their respective owners.  
http://www.DigitalCoreDesign.com  
http://www.dcd.pl  
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.