PBL 3762A/2, /4
Pin Descriptions
Refer to figure 8. Note: All pin number references in the text and figures refer to the 22-pin DIP unless otherwise specified.
DIP
PLCC
Symbol
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
21
22
23
25
27
28
2
4
5
6
7
8
9
11
HPR
RD
DT
DR
TIPX
RINGX
BGND
V
CC
Ring side of ac/dc separation capacitor C
HP
. Other end of C
HP
connects to pin 22, HPT.
Off-hook detector programming resistor R
D
in parallel with filter capacitor C
D
connect from RD to VEE.
Inputs to the ring trip comparator. With DR more positive than DT the detector output, DET (pin 14), is at
logic level low, indicating off-hook condition. The ring trip network connects to these two inputs.
The TIPX and RINGX pins connect to the tip and ring leads of the two-wire interface via overvoltage
protection components and ring relay (and optional test relay).
Ground. Should be tied together with AGND (pin 18).
+5V power supply
RINGRLY Ring relay driver output. Open collector. Sinks 50 mA to GND. Must be protected by external inductive
kick-back diode.
V
BAT
RSG
E1
E0
DET
Battery supply voltage, -24V to -58V. Negative with respect to GND (pins 7, 18).
Saturation guard programming resistor, R
SG
, connects from this terminal to V
EE
(pin 20). Refer to section
Battery feed for detailed information.
TTL compatible enable input. Enables desired detector to be gated to the DET (pin 14) output. Refer to
section Enable inputs for detailed information.
TTL compatible enable input. Enables the DET (pin 14) output when set to logic level low and disables
the DET output when set to logic level high. Refer to section Enable inputs for detailed information.
Detector output. Inputs C1 (pin 16) and C2 (pin 15) together with enable inputs E0 (pin 13) and E1 (pin
12) select one of the three detectors to be connected to the DET output. A logic low at the enabled DET
output indicates a triggered detector condition. The DET output is open collector with internal pull-up
resistor (approximately 15 kΩ to V
CC
(pin 8)).
C1 and C2 are TTL compatible inputs controlling the SLIC operating states. Refer to section Control
inputs for details.
Constant current feed is programmed by two resistors connected in series from this pin to the receive
summing node (RSN, pin 19). The resistor junction point is decoupled to GND to isolate the ac signal
components.
Ground. Should be tied together with BGND (pin 7).
Receive summing node. 1 000 times the current (dc and ac) flowing into this pin equals the metallic
(transversal) current flowing from RINGX (pin 6) to TIPX (pin 5). Programming networks for constant
current feed, two- wire impedance and receive gain connect to the receive summing node.
-5V power supply.
Transmit vf output. The ac voltage difference between TIPX (pin 5) and RINGX (pin 6), the ac metallic
voltage, is reproduced as an unbalanced GND referenced signal at VTX with a gain of one. The two-wire
impedance programming network connects between VTX and RSN (pin 19).
Tip side of ac/dc separation capacitor C
HP
. Other end of C
HP
capacitor connects to pin 1, HPR.
These pins marked VBAT are used for heat sinking and internally connected to VBAT.
TIPX
Sense
and RINGX
Sense
are internally connected to TIPX and RINGX respectively. TIPX
Sense
and
15
16
17
12
13
14
C2
C1
RDC
18
19
15
16
AGND
RSN
20
21
18
19
V
EE
VTX
22
20
3,10
26
1
HPT
VBAT
TIPX
Sense
17,24 VBAT
RINGX
Sense
RINGX
Sense
are used during manufacturing, but require no connections in SLIC applications, i.e. leave
open.
9
ERICSSON [ ERICSSON ]
