PBL 386 65/2
Pin Description
Refer to figure 8.
PLCC SSOP
Symbol
Description
Preliminary
1
2
3
7
8
9
VBAT
VBAT2
AOV
Battery supply voltage. Negative with respect to BGND.
An optional second battery voltage, connected in series with a diode, or an external powerhandling
resistor connects to this pin.
Adaptive Overhead Voltage.
If the pin is left open, then the overhead voltage is set internally to 3.1V
Peak
in off-hook and 1.4 V
Peak
in on-hook. The overhead voltage will automatically adapt to signals > 3.1V
Peak
.
If the pin is connected to AGND, then no overhead voltage is set internally. The overhead voltage adapts
automatically to 0.6 V
Peak
< signals < 6.2 V
Peak
.
Programmable Saturation Guard.
The resistive part of the DC feed characteristic is programmed by a
resistor connected from this pin to VBAT.
Low Pass
filter. Saturation guard filter capacitor connected here to filter out noise and improve PSRR.
Other end of C
LP
connects to VBAT.
Input to the ring trip comparator. With DR more positive than DT the detector output, DET, is at logic level
low, indicating off-hook condition. The ring trip network connects to this input.
Input to the ring trip comparator. With DR more positive than DT the detector output, DET, is at logic
level low, indicating off-hook condition. The ring trip network connects to this input.
-5V to VBAT power supply.
A 15 kΩ resistor should be connected between this pin and AGND.
Silent Polarity Reversal.
The polarity reversal time can be adjusted with a capacitor connected to AGND.
If pin is left open: Shortest polarity reversal time.
Prog. Line Current,
the constant current part of the DC feed characteristic is programmed by a resistor
connected from this pin to AGND.
Programmable Loop Detector
threshold. The loop detection threshold is programmed by a resistor
connected from this pin to AGND.
+5 V power supply.
C1, C2 and C3 are digital inputs
Controlling
the SLIC operating states. Refer to section
Operating states for details.
No Connect.
Must be left open.
Detector
output. Active low when indicating loop or ring trip detection, active high when indicating ground
key detection
Receive Summing Node.
400 times the current flowing into this pin equals the metallic (transversal)
current flowing from RINGX to TIPX. Programming networks for two-wire impedance and receive gain
connect to the receive summing node.
Analog Ground,
should be tied together with BGND.
Transmit vf output. The ac voltage difference between TIPX and RINGX, the ac metallic voltage, is
reproduced as an unbalanced GND referenced signal at VTX with a gain of -0.5. The two-wire
impedance programming network connects between VTX and RSN.
Ring Relay
driver output.
Tip Sense
should be connected to TIPX.
No Connect.
Must be left open.
High Pass
connection for ac/dc separation capacitor C
HP
. Other end of C
HP
connects to RINGX.
The TIPX and RINGX pins connect to the tip and ring leads of the two-wire interface via overvoltage
protection components and ring relay (and optional test relay).
Battery Ground,
should be tied together with AGND.
The TIPX and RINGX pins connect to the tip and ring leads of the two-wire interface via overvoltage
protection components and ring relay (and optional test relay).
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
10
11
12
13
16
17
18
19
20
21
22
23
24
14
25
26
PSG
LP
DT
DR
VEE
REF
SPR
PLC
PLD
VCC
C3
C2
C1
NC
DET
RSN
}
20
21
27
28
AGND
VTX
22
23
24
25
26
27
28
1
2
15
3
4
5
6
RRLY
TS
NC
HP
RINGX
BGND
TIPX
8
ERICSSON [ ERICSSON ]
