PBM99080/32MG 参数 Datasheet PDF下载

PBM 990 80

Static data

Unless otherwise stated: V

DDCORE

& V

DDPLL

& V

DDIO1+2+4

= 2.5V; V

DDIO3

& V

DDFL

= 2.7V; VSS = 0V; T

AMB

= -40 .. +85°C

Parameter

Supply voltage Baseband core

Supply voltage Baseband PLL

Supply voltage Flash memory

Supply voltage IO group 1

Supply voltage IO group 2

Supply voltage IO group 3

Condition

Must always be

connected to V

DDPLL

Must always be

connected to V

DDCORE

Must always be

connected to V

DDIO3

Symbol

V

DDCORE

V

DDPLL

V

DDFL

V

DDIO1

V

DDIO2

V

DDIO3

V

DDIO4

V

IL

V

IH

V

IT+

V

IT

-

V

HYS

R

PU

R

PD

I

LI

V

OL

V

OH

I

OT

Min

2.3

2.3

2.6

6)

V

DDCORE

V

DDCORE

2.6

6)

V

DDCORE

V

SSIO

– 0.3

0.7* V

DDCORE

Typ

2.5

2.5

3.3

2.5

3.3

3.3

2.5

Max

2.7

2.7

3.6

3.6

3.6

3.6

3.6

0.3×V

DDCORE

V

DDIO

+ 0.3

1.60

Unit

V

V

V

V

V

V

V

V

V

V

V

V

80

40

+1

V

SSIO

+ 0.1

V

DDIO

+1

kΩ

kΩ

µA

µA

V

V

µA

µA

Must always be

connected to V

DDFL

Supply voltage IO group 4

Low level input voltage, digital input

Guaranteed input low

High level input voltage, digital input

Guaranteed input high

Schmitt trigger input threshold voltage V

DDIO1

= 3.3V

V

DDCORE

= 2.5V

Schmitt trigger input threshold voltage V

DDIO1

= 3.3V

V

DDCORE

= 2.5V

Schmitt trigger input Hysteresis

V

DDIO1

= 3.3V

(V

T-

- V

T-

)

V

DDCORE

= 2.5V

Input pin internal pull-up resistor

Input pin internal pull-down resistor

Input leakage current, any digital input V

I

= V

SSIO

or bidirectional pin in input mode

V

I

= V

DDIO

Low level output voltage

I

OL

= 800 µA

High level output voltage

I

OH

= -800 µA

Output leakage current, tri-state

V

O

= V

SSIO

V

O

= V

DDIO

1)

1.45

0.90

0.45

30

10

-1

0

V

DDIO

- 0.1

-1

0.95

0.5

50

20

All V

DDIO

& V

DDFL

supply voltages must be powered on prior to or simultaneously as the V

DDCORE

& V

DDPLL

supply voltage. Deviations

from this power up sequence might damage the device.

If the V

DDCORE

& V

DDPLL

voltage is greater than either of the V

DDIO

& V

DDFL

voltages by about 0.5V or more, then PBM 990 80 will not

work. This is because the inputs to the baseband core from the pins will not be sufficiently high level to drive the baseband core

gates. The level shifter between baseband core and baseband I/O is only designed to shift from a low core to a high I/O.

If the V

DDCORE

& V

DDPLL

voltage is off, but the V

DDIO

& V

DDFL

voltage is left on, then this will cause PBM 990 80 to drive out a logic

low on all output pins.

All PBM 990 80 input and bidirectional pins can be connected to any external driving circuit of max 3.6V before turning on the

supply, without the device being damaged. However it cannot be guaranteed that PBM 990 80 does not load the external driver in

this case, unless the baseband core supply voltage is completely discharged prior to this event.

The input stage on all digital inputs is designed with 3.3V I/O transistors, but is supplied by V

DDCORE

.

PBM 990 80 with 8 Mbit Flash memory option only supports V

DDIO3

& V

DDFL

down to 2.7 V. A new product version supporting V

DDIO3

& V

DDFL

down to 2.6 V will be available Q3-02

2)

3)

4)

5)

6)

4