Input and Output Impedance
Both the source impedance of the power feeding and the load
impedance will interact with the impedance of the DC/DC power
module.
It is most important to have the ratio between L and C as low as
possible, i.e. a low characteristic impedance, both at the input and
output, as the power modules have a low energy storage capability.
Use an electrolytic capacitor across the input if the source induct-
ance is higher than 10
mH.
Their equivalent series resistance to-
gether with the capacitance acts as a lossless damping filter.
Suitable capacitor values are in the range 10–100
mF.
Figure 2
Synchronization (Sync)
It is possible to synchronize the switching frequency to an external
symmetrical clock signal. The input can be driven by an TTL-
compatible output and referenced to the input pin 17.
Output Voltage Adjust (V
adj
)
Output voltage, V
O
, can be adjusted by using an external resistor
or other external circuitry. If other circuitry is used, the slew rate
has to be limited to maximum 5 V/ms. If pins 8 and 9 are not
connected together the output will decrease to a low value. To
increase V
O
a resistor should be connected between pin 8/9 and 17,
and to decrease V
O
a resistor should be connected between pin 8
and 9 (see fig. 3).
To increase output voltage:
R
ounom
= 4.3×(15.25-V
O
)/(V
O
-V
I
) kW
V
I
is the initial output voltage when pin 8 and 9 are connected,
V
O
is the desired output voltage.
To decrease output voltage:
R
odnom
=16.5×(V
I
-V
O
)/(V
O
-8.85) kW
V
I
is the initial output voltage when pin 8 and 9 are connected,
V
O
is the desired output voltage.
Characteristics
High level
Threshold
Low level
Sink current
Sync. frequency
*)
min
2.2
typ
max
6.5
unit
V
V
V
mA
kHz
level
*)
1.2
0
520
1.7
2.2
0.4
1.5
688
Rise time <10ns
Parallel Operation
Paralleling of several converters is easily accomplished by direct
connection of the output voltage terminal pins. The load regula-
tion characteristic is specifically designed for optimum paralleling
performance. Load sharing between converters will be within
±10%. It is recommended not to exceed P
O
= n × 0.9 × P
O max
,
where P
Omax
is the maximum converter output power and n the
number of paralleled converters, to prevent overloading any of the
converters and thereby decreasing the reliability performance.
Order Info
Version
Surface mount
Through hole
Part No.
PKF 4121A SI
PKF 4121A PI
Figure 3
Current Limiting Protection (I
lim
)
The output power is limited at loads above the output current
limiting threshold (I
lim
), specified as a minimum value.
Capacitive Load
The PKF series has no maximum limit for capacitive load on the
output. The power module may operate in current limiting mode
during start-up, affecting the ramp-up and the start-up time. For
optimum start performance we recommend maximum 100
mF/A
of
I
O
. Connect capacitors at the point of load for best performance.
Information given in this data sheet is believed to be accurate and reliable. No respon-
sibility is assumed for the consequences of its use nor for any infringement
of patents or other rights of third parties which may result from its use.
No license is granted by implication or otherwise under any patent or patent rights of
Ericsson Microelectronics. These products are sold only according to Ericsson
Microelectronics’ general conditions of sale, unless otherwise confirmed in writing.
Specifications subject to change without notice.
EN/LZT 146 84 R1A © Ericsson Microelectronics AB, May 2001
7
ERICSSON [ ERICSSON ]
