MP7529B
DIGITAL INTERFACE
The digital inputs are designed to be both TTL and 5 V CMOS
compatible. All logic inputs are static protected MOS gates with
typical input currents of less than 10nA.
The control input DAC A/DAC B selects which DAC can ac-
cept data from the input port. Inputs CS and WR control the op-
erating mode of the selected DAC (Table
1.).
When CS and WR
t
CS
CS
t
AS
DAC A/
DAC B
VALID
t
WR
WR
t
DS
DB7-DB0
VALID
t
DH
t
AH
t
CH
are both low the selected DAC is in the write mode. The input
data latches of the selected DAC are transparent and its analog
output responds to activity on DB0-DB7 (Write mode). The se-
lected DAC latch retains the data which was present on
DB0-DB7 just prior to CS or WR assuming a high state. Both
analog outputs remain at the values corresponding to the data in
their respective latches (Hold mode).
DAC A/
DAC B
L
H
X
X
L = Low State
CS
WR
DAC A
WRITE
HOLD
HOLD
HOLD
X = Don’t Care
DAC B
HOLD
WRITE
HOLD
HOLD
L
L
L
L
H
X
X
H
H = High State
NOTE:
1. Timing measured from (V
IH
+ V
IL
) /2
Figure 1. Write Cycle Timing Diagram
Table 1. DAC’s Mode Selection
MICROPROCESSOR INTERFACE
NOTE:
8085 instruction shld (store H & L direct) can update
both DACS with data from H and L registers
A0-A15
A**
V
MA
CPU
6800
ADDRESS
DECODE
LOGIC
Address Bus
DAC A/DAC B
CS
A+1***
DAC A
A8-A15
A**
CPU
8085
WR
ALE
AD0–AD7
ADDRESS
DECODE
LOGIC
Address Bus
DAC A/DAC B
CS
A+1***
LATCH
8212
DAC A
φ
2
WR MP7529B*
DAC B
DB0
DB7
Data Bus
WR
DB0
DB7
MP7529B*
DAC B
D0–D7
ADDR/Data Bus
*Analog circuitry has been omitted for clarity
**A = Decoded 7529B DAC A Address
***A + 1 = Decoded 7529B DAC B Address
*Analog circuitry has been omitted for clarity
**A = Decoded 7529B DAC A Address
***A + 1 = Decoded 752B9 DAC B Address
Figure 2. MP7529B Dual DAC to 6800
CPU Interface
Figure 3. MP7529B Dual DAC to 8085
CPU Interface
Rev. 2.00
5
EXAR [ EXAR CORPORATION ]
