PRELIMINARY
FEBRUARY 2007
XRK32308
3.3V ZERO DELAY BUFFER
REV. P1.0.3
GENERAL DESCRIPTION
FUNCTIONAL DESCRIPTION
XRK32308 is a 3.3V Zero Delay Buffer designed to
distribute high-speed clocks in PC, workstation,
datacom, telecom, and other high-performance
applications.
The part has an on-chip PLL which locks to an input
clock presented on the REF pin. The PLL feedback is
required to be driven into the FB pin, and can be
obtained from one of the outputs. The input-to-output
skew is guaranteed to be less than 350 ps, and
output-to-output skew is guaranteed to be less than
200 ps.
XRK32308 has two banks of four outputs each.
These can be controlled by the Select inputs as
shown in Table 2, “Select Input Decoding,” on page 2.
If all output clocks are not required, Bank B can be
three-stated. The select inputs also allow the input
clock to be directly applied to the output for chip and
system testing purposes.
Multiple XRK32308 devices can accept the same
input clock and distribute it in a system. In this case,
the skew between the outputs of two devices is
guaranteed to be less than 700 ps.
XRK32308 devices are available in five different
configurations, as shown in Table 3, “Available
The XRK32308–1 is the base part, where the output
frequencies equal the reference if there is no counter
in the feedback path.
The XRK32308–1H is the high-drive version of the –
1. Rise and fall times on this device are faster.
The XRK32308–2 allows the user to obtain 1X, and
2X or X/2 depending on which Bank sources the FB
signal.
The XRK32308–3 allows the user to obtain 4X and
2X frequencies or 1X and 2X.
The XRK32308–4 enables the user to obtain 2X
clocks on all outputs.
The XRK32308–5H is a high-drive version with REF/
2 on both banks.
FEATURES
•
Zero input-output propagation delay, adjustable by
capacitive load on FB input
•
Multiple configurations, see “Available XRK32308
Configurations” table
•
Multiple low-skew outputs
•
Two banks of four outputs, three-stateable by two
select inputs
•
10-MHz to 120-MHz operating range
•
75ps typical cycle-to-cycle jitter (15pF, 66MHz)
•
Space-saving 16-pin 150-mil SOIC package, 16-pin
TSSOP or 16-pin QFN
•
3.3V operation
•
Industrial and commercial temperature available
F
IGURE
1. B
LOCK
D
IAGRAM AND
P
IN
C
ONFIGURATION OF THE
XRK32308
/2
PLL
REF
/2
Extra Divider (-3, -4)
Extra Divider (-5H)
S2
S1
MUX
FB
QA0
QA1
QA2
QA3
QA0 REF
FB
QA3
REF
QA0
QA1
V
DD
GND
QB0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
FB
QA3
QA2
V
DD
GND
QB3
QB2
S1
QA1
VDD
GND
QB0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
QA2
VDD
GND
QB3
Select Input
Decoding
/2
QB0
QB1
Extra Divider (-2, -3)
QB2
QB3
QB1
S2
QB1
S2
S1
QB2
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
EXAR [ EXAR CORPORATION ]
