欢迎访问ic37.com |
会员登录 免费注册
发布采购

XRK32309CG-1H 参数 Datasheet PDF下载

XRK32309CG-1H图片预览
型号: XRK32309CG-1H
PDF下载: 下载PDF文件 查看货源
内容描述: 低成本3.3V零延迟缓冲器 [LOW-COST 3.3V ZERO DELAY BUFFER]
分类和应用: 时钟驱动器逻辑集成电路光电二极管
文件页数/大小: 13 页 / 335 K
品牌: EXAR [ EXAR CORPORATION ]
 浏览型号XRK32309CG-1H的Datasheet PDF文件第4页浏览型号XRK32309CG-1H的Datasheet PDF文件第5页浏览型号XRK32309CG-1H的Datasheet PDF文件第6页浏览型号XRK32309CG-1H的Datasheet PDF文件第7页浏览型号XRK32309CG-1H的Datasheet PDF文件第9页浏览型号XRK32309CG-1H的Datasheet PDF文件第10页浏览型号XRK32309CG-1H的Datasheet PDF文件第11页浏览型号XRK32309CG-1H的Datasheet PDF文件第12页  
XRK32309
LOW-COST 3.3V ZERO DELAY BUFFER
PRELIMINARY
REV. P1.0.1
T
ABLE
10: S
WITCHING
C
HARACTERISTICS FOR
XRK32309SI-1 I
NDUSTRIAL
T
EMPERATURE
D
EVICES[7]
P
ARAMETER
t
1
DC
t
3
t
4
t
5
t
6A
N
AME
Output Frequency
30-pF load
10-pF load
Measured at 1.4V, F
OUT
=66.67MHz
Measured between 0.8V and 2.0V
Measured between 0.8V and 2.0V
All outputs equally loaded
T
EST
C
ONDITIONS
M
IN
10
10
40.0
-
-
-
-
T
YP
-
M
AX
100
120
60.0
2.50
2.50
250
±350
U
NIT
MHz
MHz
%
ns
ns
ps
ps
Duty Cycle
[6]
= t
2
÷
t
1
Rise Time
[6]
Fall Time
[6]
Output to Output Skew
[6]
50.0
-
-
-
0
Delay, REF Rising Edge to Measured at V
DD
/2
FB Rising Edge
[6]
Delay, REF Rising Edge to Measured at V
DD
/2. Measured in PLL
Bypass Mode
FB Rising Edge
[6]
Device to Device Skew
[6]
Cycle to Cycle Jitter
[6]
PLL Lock Time
[6]
Measured at V
DD
/2 on the FB pins of
devices
Measured at 66.67MHz, loaded outputs
Stable power suppy, valid clock
presented on REF pin
t
6B
1
5
8.7
ns
t
7
t
J
t
LOCK
-
0
700
ps
-
-
-
-
200
1.0
ps
ms
T
ABLE
11: S
WITCHING
C
HARACTERISTICS FOR
XRK32309SI-1H I
NDUSTRIAL
T
EMPERATURE
D
EVICES[7]
P
ARAMETER
t
1
N
AME
Output Frequency
30-pF load
10-pF load
Measured at 1.4V, F
OUT
=66.67MHz
Measured at 1.4V, F
OUT
<50.0MHz
Measured between 0.8V and 2.0V
Measured between 0.8V and 2.0V
All outputs equally loaded
T
EST
C
ONDITIONS
M
IN
10
10
40.0
45.0
-
-
-
-
T
YP
-
M
AX
100
120
60.0
55.0
1.50
1.50
250
±350
U
NIT
MHz
MHz
%
%
ns
ns
ps
ps
50.0
50.0
-
-
-
0
DC
t
3
t
4
t
5
t
6A
t
6B
t
7
t
8
Duty Cycle
[6]
= t
2
÷
t
1
Rise Time
[6]
Fall Time
[6]
Output to Output Skew
[6]
FB Rising Edge
[6]
Delay, REF Rising Edge to Measured at V
DD
/2
Delay, REF Rising Edge to Measured at V
DD
/2. Measured in PLL
Bypass Mode
FB Rising Edge
[6]
Device to Device Skew
[6]
Output Slew Rate
[6]
Measured at V
DD
/2 on the FB pins of
devices
Measured between 0.8V and 2.0V using
Test Circuit #2
1
5
8.7
ns
-
0
700
ps
1
-
-
v/ns
8