XRT83SL38
OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
PRELIMINARY
and G.823; TR-TSY-000499; ANSI T1.403 and
T1.408; ETSI 300-166 and AT&T Pub 62411
•
Supports both
Hardware
and
Host
(parallel Micro-
processor) interface for programming
•
Programmable Interrupt
•
Low power dissipation
REV. P1.1.0
•
Logic inputs accept either 3.3V or 5V levels
•
Single 3.3V Supply Operation
•
208 pin TQFP or 225 ball BGA package
•
-40°C to +85°C Temperature Range
ORDERING INFORMATION
P
ART
N
UMBER
XRT83SL38IV
XRT83SL38IB
P
ACKAGE
208 Lead TQFP (28 x 28 x 1.4mm)
225 Ball BGA
O
PERATING
T
EMPERATURE
R
ANGE
-40
°
C to +85
°
C
-40
°
C to +85
°
C
F
IGURE
3. P
IN
O
UT OF THE
XRT83SL38
R N EG_3 / LC V_3
R CLK_3
R LO S_3
TN EG_3 / CO DES_3
TPOS_3 / TD ATA_3
TCLK_3
TCLK_2
TPOS_2 / TD ATA_2
TN EG_2 / CO DES_2
DMO _3
JASEL0
JASEL1
TXON _0
TXON _1
TXON _2
TXON _3
A[7] / LOOP1_3
A[6] / LOOP0_3
A[5] / LOOP1_2
A[4] / LOOP0_2
A[3] / LOOP1_1
A[2] / LOOP0_1
A[1] / LOOP1_0
A[0] / LOOP0_0
DVDD PreD river
D VD D Driver
D VD D
DG ND
D GN D D river
DG ND PreD river
C LKSEL0
C LKSEL1
C LKSEL2
W R _R /W / EQC 0
R D_D S / EQC 1
ALE_AS / EQC 2
CS / EQC 3
R DY_D TACK / EQC 4
TAO S_0
TAO S_1
TAO S_2
TAO S_3
DMO _0
TN EG_1 / CO DES_1
TPOS_1 / TD ATA_1
TCLK_1
TCLK_0
TPOS_0 / TD ATA_0
TN EG_0 / CO DES_0
R LO S_0
R CLK_0
R N EG_0 / LC V_0
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
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185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
R POS_3 / RD ATA_3
R VDD _3
R TIP_3
R RIN G_3
R GN D_3
TGND _3
TTIP_3
TVDD _3
TRIN G_3
D MO_2
TRIN G_2
TVDD _2
TTIP_2
TGND _2
R GN D_2
R RIN G_2
R TIP_2
R VDD _2
R POS_2 / RD ATA_2
R NEG _2 / LC V_2
R CLK_2
R LOS_2
GAUG E
PTS1 / R CLKE
AG ND Bias
D GN D
µ
P
D VDD
µ
P
AVDD Bias
PTS2 / TCLKE
IN T / TRATIO
R LOS_6
R CLK_6
R NEG _6 / LC V_6
R POS_6 / RD ATA_6
R VDD _6
R TIP_6
R RIN G_6
R GN D_6
TGND _6
TTIP_6
TVDD _6
TRIN G_6
D MO_6
TRIN G_7
TVDD _7
TTIP_7
TGND _7
R GN D_7
R RIN G_7
R TIP_7
R VDD _7
R POS_7 / RD ATA_7
XRT83SL38
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
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71
70
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68
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66
65
64
63
62
61
60
59
58
57
56
55
54
53
R N EG_7/LCV_7
R C LK_7
R LO S_7
TN EG_7 / CO DES_7
TPO S_7 / TDATA_7
TC LK_7
TC LK_6
TPO S_6 / TDATA_6
TN EG_6 / CO DES_6
D MO _7
µ
PC LK / ATAO S
TXO N_7
TXO N_6
TXO N_5
TXO N_4
R XM UTE
IC T
TEST
TER SEL0
TER SEL1
TXTSEL
R XTSEL
R XR ES0
R XR ES1
H W _H OST
D VD D
D VD D
D GN D
D GN D
R ESET
D [0] / LOOP0_7
D [1] / LOOP1_7
D [2] / LOOP0_6
D [3] / LOOP1_6
D [4] / LOOP0_5
D [5] / LOOP1_5
D [6] / LOOP0_4
D [7] / LOOP1_4
TAO S_7
TAO S_6
TAO S_5
TAO S_4
D MO _4
TN EG_5 / CO DES_5
TPO S_5 / TDATA_5
TC LK_5
TC LK_4
TPO S_4 / TDATA_4
TN EG_4 / CO DES_4
R LO S_4
R C LK_4
R N EG_4 / LC V_4
RPO S_0 / R DATA_0
R VD D_0
R TIP_0
R RIN G_0
R GN D_0
TGN D_0
TTIP_0
TVD D_0
TRIN G_0
D MO_1
TRIN G_1
TVD D_1
TTIP_1
TGN D_1
R GN D_1
R RIN G_1
R TIP_1
R VD D_1
RPO S_1 / R DATA_1
R N EG_1 / LC V_1
RC LK_1
R LOS_1
MC LKOU T
VDD PLL_1
VDD PLL_2
MC LKE1
MC LKT1
G ND PLL_1
G ND PLL_2
SR/D R
R LOS_5
RC LK_5
R N EG_5 / LC V_5
RPO S_5 / R DATA_5
R VD D_5
R TIP_5
R RIN G_5
R GN D_5
TGN D_5
TTIP_5
TVD D_5
TRIN G_5
D MO_5
TRIN G_4
TVD D_4
TTIP_4
TGN D_4
R GN D_4
R RIN G_4
R TIP_4
R VD D_4
RPO S_4 / R DATA_4
1
2
3
4
5
6
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9
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3
EXAR [ EXAR CORPORATION ]
