XRT86L30
SINGLE T1/E1/J1 FRAMER/LIU COMBO
JANUARY 2008
REV. 1.0.1
GENERAL DESCRIPTION
The XRT86L30 is a single channel 1.544 Mbit/s or
2.048 Mbit/s DS1/E1/J1 framer and LIU integrated
solution featuring R
3
technology (Relayless,
Reconfigurable, Redundancy).
The physical
interface is optimized with internal impedance, and
with the patented pad structure, the XRT86L30
provides protection from power failures and hot
swapping.
The XRT86L30 contains an integrated DS1/E1/J1
framer and LIU which provide DS1/E1/J1 framing and
error accumulation in accordance with ANSI/ITU_T
specifications. The framer has a framing synchronizer
and transmit-receive slip buffers. The slip buffers can
be independently enabled or disabled as required
and can be configured to frame to the common DS1/
E1/J1 signal formats.
The Framer block contains a Transmit and Receive
T1/E1/J1 Framing function. There are 3 Transmit
HDLC controllers which encapsulate contents of the
Transmit HDLC buffers into LAPD Message frames.
There are 3 Receive HDLC controllers which extract
the payload content of Receive LAPD Message
frames from the incoming T1/E1/J1 data stream and
write the contents into the Receive HDLC buffers.
The framer also contains a Transmit and Overhead
Data Input port, which permits Data Link Terminal
Equipment direct access to the outbound T1/E1/J1
frames. Likewise, a Receive Overhead output data
port permits Data Link Terminal Equipment direct
access to the Data Link bits of the inbound T1/E1/J1
frames.
The XRT86L30 fully meets all of the latest T1/E1/J1
specifications:
ANSI T1/E1.107-1988, ANSI T1/
E1.403-1999, ANSI T1/E1.231-1993, ANSI T1/
E1.408-1990, AT&T TR 62411 (12-90) TR54016, and
ITU G-703, G.704, G706 and G.733, AT&T Pub.
43801, and ETS 300 011, 300 233, JT G.703, JT
G.704, JT G706, I.431. Extensive test and diagnostic
functions include Loop-backs, Boundary scan,
Pseudo Random bit sequence (PRBS) test pattern
generation, Performance Monitor, Bit Error Rate
(BER) meter, forced error insertion, and LAPD
unchannelized data payload processing according to
ITU-T standard Q.921.
Applications and Features (next page)
F
IGURE
1. XRT86L30 1-
CHANNEL
DS1 (T1/E1/J1) F
RAMER
/LIU C
OMBO
External Data
Link Controller
Local PCM
Highway
XRT86L30
Tx Overhead In
Rx Overhead Out
1:2 Turns Ratio
TTIP
Tx Serial
Data In
Tx Serial
Clock
2-Frame
Slip Buffer
Elastic Store
Tx Framer
Tx LIU
Interface
LLB
LB
TRING
ST-BUS
Rx Serial
Data Out
Rx Serial
Clock
2-Frame
Slip Buffer
Elastic Store
RTIP
1:1 Turns Ratio
Rx Framer
Rx LIU
Interface
RRING
PRBS
Generator &
Analyser
Performance
Monitor
HDLC/LAPD
Controllers
LIU &
Loopback
Control
RxLOS
8kHz sync
OSC
Signaling &
Alarms
JTAG
DMA
Interface
Line Side
Microprocessor
Interface
Back Plane
1.544-16.384 Mbit/s
3
System (Terminal) Side
TxON
Memory
INT
D[7:0]
A[11:0]
µP
Select
4 WR
ALE_AS
RD
RDY_DTACK
Intel/Motorola µP
Configuration, Control &
Status Monitor
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
EXAR [ EXAR CORPORATION ]
