74F381
Unit Loading/Fan Out
Pin Names
A
0
–A
3
B
0
–B
3
S
0
–S
2
C
n
G
P
F
0
–F
3
Description
A Operand Inputs
B Operand Inputs
Function Select Inputs
Carry Input
Carry Generate Output (Active LOW)
Carry Propagate Output (Active LOW)
Function Outputs
U.L.
HIGH/LOW
1.0/3.0
1.0/3.0
1.0/1.0
1.0/4.0
50/33.3
50/33.3
50/33.3
Input I
IH
/I
IL
Output I
OH
/I
OL
20
µA/−1.8
mA
20
µA/−1.8
mA
20
µA/−0.6
mA
20
µA/−2.4
mA
−1
mA/20 mA
−1
mA/20 mA
−1
mA/20 mA
Functional Description
Signals applied to the Select inputs S
0
–S
2
determine the
mode of operation, as indicated in the Function Select
Table. An extensive listing of input and output levels is
shown in the Truth Table. The circuit performs the arith-
metic functions for either active HIGH or active LOW oper-
ands, with output levels in the same convention. In the
Subtract operating modes, it is necessary to force a carry
(HIGH for active HIGH operands, LOW for active LOW
operands) into the C
n
input of the least significant package.
The Carry Generate (G) and Carry Propagate (P) outputs
supply input signals to the 74F182 carry lookahead gener-
ator for expansion to longer word length, as shown in Fig-
ure 2. Note that an 74F382 ALU is used for the most
significant package. Typical delays for Figure 2 are given in
Figure 1.
Function Select Table
Select
S
0
L
H
L
H
L
H
L
H
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
S
1
L
L
H
H
L
L
H
H
S
2
L
L
L
L
H
H
H
H
Operation
Clear
B Minus A
A Minus B
A Plus B
A⊕B
A
+
B
AB
Preset
Toward
Path Segment
F
A
i
or B
i
to P
P
i
to C
n
+
('F182)
C
n
to F
C
n
or C
n
+
4, OVR
Total Delay
7.2 ns
6.2 ns
8.1 ns
—
21.5 ns
Output
C
n
+
4, OVR
7.2 ns
6.2 ns
—
8.0 ns
21.4 ns
FIGURE 1. 16-Bit Delay Tabulation
FIGURE 2. 16-Bit Lookahead Carry ALU Expansion
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