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74VHC139 参数 Datasheet PDF下载

74VHC139图片预览
型号: 74VHC139
PDF下载: 下载PDF文件 查看货源
内容描述: 双路2至4解码器/多路解复用器 [Dual 2-to-4 Decoder/Demultiplexer]
分类和应用: 解码器解复用器
文件页数/大小: 6 页 / 76 K
品牌: FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
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74VHC139 Dual 2-to-4 Decoder/Demultiplexer
November 1992
Revised April 1999
74VHC139
Dual 2-to-4 Decoder/Demultiplexer
General Description
The VHC139 is an advanced high speed CMOS Dual 2-to-
4 Decoder/Demultiplexer fabricated with silicon gate
CMOS technology. It achieves the high speed operation
similar to equivalent Bipolar Schottky TTL while maintain-
ing the CMOS low power dissipation.
The active LOW enable input can be used for gating or it
can be used as a data input for demultiplexing applications.
When the enable input is held HIGH, all four outputs are
fixed at a HIGH logic level independent of the other inputs.
An input protection circuit ensures that 0V to 7V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery back up. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
Features
s
High Speed: t
PD
=
5.0 ns (typ) at T
A
=
25°C
s
Low power dissipation: I
CC
=
4
µA
(Max.) at T
A
=
25°C
s
High noise immunity: V
NIH
=
V
NIL
=
28% V
CC
(Min.)
s
Power down protection is provided on all inputs
s
Pin and function compatible with 74HC139
Ordering Code:
Order Number
74VHC139M
74VHC139SJ
74VHC139MTC
74VHC139N
Package Number
M16A
M16D
MTC16
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Description
Pin Names
A
0
, A
1
E
O
0
–O
3
Description
Address Inputs
Enable Inputs
Outputs
Truth Table
Inputs
E
H
L
L
L
L
A
0
X
L
H
L
H
A
1
X
L
L
H
H
O
0
H
L
H
H
H
Outputs
O
1
H
H
L
H
H
O
2
H
H
H
L
H
O
3
H
H
H
H
L
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
© 1999 Fairchild Semiconductor Corporation
DS011521.prf
www.fairchildsemi.com