CD4001BC/CD4011BC Quad 2-Input NOR Buffered B Series Gate • Quad 2-Input NAND Buffered B Series Gate
October 1987
Revised March 2002
CD4001BC/CD4011BC
Quad 2-Input NOR Buffered B Series Gate •
Quad 2-Input NAND Buffered B Series Gate
General Description
The CD4001BC and CD4011BC quad gates are monolithic
complementary MOS (CMOS) integrated circuits con-
structed with N- and P-channel enhancement mode tran-
sistors. They have equal source and sink current
capabilities and conform to standard B series output drive.
The devices also have buffered outputs which improve
transfer characteristics by providing very high gain.
All inputs are protected against static discharge with diodes
to V
DD
and V
SS
.
Features
s
Low power TTL:
Fan out of 2 driving 74L compatibility:
s
5V–10V–15V parametric ratings
s
Symmetrical output characteristics
s
Maximum input leakage 1
µ
A at 15V over full
temperature range
or 1 driving 74LS
Ordering Code:
Order Number
CD4001BCM
CD4001BCSJ
CD4001BCN
CD4011BCM
CD4011BCN
Package Number
M14A
M14D
N14A
M14A
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
Pin Assignments for DIP, SOIC and SOP
CD4001BC
Pin Assignments for DIP and SOIC
CD4011BC
Top View
Top View
© 2002 Fairchild Semiconductor Corporation
DS005939
www.fairchildsemi.com
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