CD4023BC Buffered Triple 3-Input NAND Gate
October 1987
Revised August 2000
CD4023BC
Buffered Triple 3-Input NAND Gate
General Description
These triple gates are monolithic complementary MOS
(CMOS) integrated circuits constructed with N- and P-
channel enhancement mode transistors. They have equal
source and sink current capabilities and conform to stan-
dard B series output drive. The devices also have buffered
outputs which improve transfer characteristics by providing
very high gain. All inputs are protected against static dis-
charge with diodes to V
DD
and V
SS
.
Features
s
Wide supply voltage range:
s
Low power TTL compatibility:
fan out of 2 driving 74L or 1 driving 74LS
s
5V–10V–15V parametric ratings
s
Symmetrical output characteristics
s
Maximum input leakage 1
µ
A at 15V over full
temperature range
3.0V to 15V
s
High noise immunity: 0.45 V
DD
(typ)
Ordering Code:
Order Number
CD4023BCM
CD4023BCS
CD4023BCN
Package Number
M14A
M14D
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” tot he ordering code.
Connection Diagram
Block Diagram
1
/
3
Device Shown
Top View
*All Inputs Protected by Standard CMOS Input Protection Circuit.
© 2000 Fairchild Semiconductor Corporation
DS005956
www.fairchildsemi.com
FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
