CD4070BC Quad 2-Input EXCLUSIVE-OR Gate
October 1987
Revised January 1999
CD4070BC
Quad 2-Input EXCLUSIVE-OR Gate
General Description
The CD4070BC employs complementary MOS (CMOS)
transistors to achieve wide power supply operating range,
low power consumption, and high noise margin, the
CD4070BC provide basic functions used in the implemen-
tation of digital integrated circuit systems. The N- and P-
channel enhancement mode transistors provide a symmet-
rical circuit with output swing essentially equal to the supply
voltage. No DC power other than that caused by leakage
current is consumed during static condition. All inputs are
protected from damage due to static discharge by diode
clamps to V
DD
and V
SS
.
Features
s
Wide supply voltage range:
s
High noise immunity:
3.0V to 15V
0.45 V
DD
typ.
s
Low power TTL compatibility:
Fan out of 2 driving 74L or 1 driving 74LS
s
Pin compatible to CD4030A
Equivalent to MM74C86 and MC14070B
Ordering Code:
Order Number
CD4070BCM
CD4070BCN
Package Number
M14A
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignments for SOIC and DIP
Truth Table
Inputs
A
L
L
H
H
B
L
H
L
H
Outputs
Y
L
H
H
L
Top View
© 1999 Fairchild Semiconductor Corporation
DS005976.prf
www.fairchildsemi.com
FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
