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FDC6321C 参数 Datasheet PDF下载

FDC6321C图片预览
型号: FDC6321C
PDF下载: 下载PDF文件 查看货源
内容描述: 双N和P通道FET数字 [Dual N & P Channel , Digital FET]
分类和应用: 晶体小信号场效应晶体管开关光电二极管
文件页数/大小: 11 页 / 274 K
品牌: FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
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April 1999
FDC6321C
Dual N & P Channel , Digital FET
General Description
These dual N & P Channel logic level enhancement mode
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance. This device has been designed
especially for low voltage applications as a replacement for
digital transistors in load switching applications. Since bias
resistors are not required this dual digital FET can replace
several digital transistors with different bias resistors.
Features
N-Ch 25 V, 0.68 A, R
DS(ON)
= 0.45
@ V
GS
= 4.5 V
P-Ch -25 V, -0.46 A, R
DS(ON)
= 1.1
@ V
GS
= -4.5 V.
Very low level gate drive requirements allowing direct
operation in 3 V circuits. V
GS(th)
< 1.0V.
Gate-Source Zener for ESD ruggedness.
>6kV Human Body Model
Replace multiple dual NPN & PNP digital transistors.
SOT-23
SuperSOT
TM
-6
Mark:.321
SuperSOT
TM
-8
SO-8
SOT-223
SOIC-16
D2
S1
D1
4
3
G2
5
2
SuperSOT
TM
-6
S2
G1
6
1
Absolute Maximum Ratings
Symbol
Parameter
T
A
= 25
o
C unless other wise noted
N-Channel
P-Channel
Units
V
DSS
, V
CC
V
GSS
, V
IN
I
D
, I
O
P
D
T
J
,T
STG
ESD
Drain-Source Voltage, Power Supply Voltage
Gate-Source Voltage,
Drain/Output Current
- Continuous
- Pulsed
Maximum Power Dissipation
(Note 1a)
(Note 1b)
25
8
0.68
2
0.9
0.7
-55 to 150
6
-25
-8
-0.46
-1.5
V
V
A
W
Operating and Storage Tempature Ranger
Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf / 1500 Ohm)
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
°C
kV
THERMAL CHARACTERISTICS
R
θJA
R
θJC
(Note 1a)
(Note 1)
140
60
°C/W
°C/W
© 1999 Fairchild Semiconductor Corporation
FDC6321C.RevB