FDC6506P
February 1999
FDC6506P
Dual P-Channel Logic Level PowerTrench™ MOSFET
General Description
These P-Channel logic level MOSFETs are produced using
Fairchild Semiconductor's advanced PowerTrench
process that has been especially tailored to minimize
on-state resistance and yet maintain low gate charge for
superior switching performance.
These devices have been designed to offer exceptional
power dissipation in a very small footprint for applications
where the bigger more expensive SO-8 and TSSOP-8
packages are impractical.
Features
•
-1.8 A, -30 V. R
DS(on)
= 0.170
Ω
@ V
GS
= -10 V
R
DS(on)
= 0.280
Ω
@ V
GS
= -4.5 V
•
•
•
•
Low gate charge (2.3nC typical).
Fast switching speed.
High performance trench technology for extremely
low R
DS(ON)
.
SuperSOT
TM
-6 package: small footprint (72% smaller
than standard SO-8); low profile (1mm thick).
Applications
•
Load switch
•
Battery protection
•
Power management
D2
S1
D1
4
3
5
2
G2
SuperSOT
TM
-6
S2
G1
T
A
= 25°C unless otherwise noted
6
1
Absolute Maximum Ratings
Symbol
V
DSS
V
GSS
I
D
P
D
Drain-Source Voltage
Gate-Source Voltage
Drain Current
- Continuous
- Pulsed
Parameter
Ratings
-30
(Note 1a)
Units
V
V
A
W
±
20
-1.8
-10
0.96
0.9
0.7
-55 to +150
Power Dissipation for Single Operation
(Note 1a)
(Note 1b)
(Note 1c)
T
J
, T
stg
Operating and Storage Junction Temperature Range
°
C
Thermal Characteristics
R
θ
JA
R
θ
JC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
130
60
°
C/W
°
C/W
Package Outlines and Ordering Information
Device Marking
.
506
©1999
Fairchild Semiconductor Corporation
Device
FDC6506P
Reel Size
7’’
Tape Width
8mm
Quantity
3000 units
FDC6506P Rev. C
FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
