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FDG6313N 参数 Datasheet PDF下载

FDG6313N图片预览
型号: FDG6313N
PDF下载: 下载PDF文件 查看货源
内容描述: 双N通道FET数字 [Dual N-Channel, Digital FET]
分类和应用: 晶体晶体管开关光电二极管
文件页数/大小: 5 页 / 60 K
品牌: FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
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April 2002
FDG6313N
Dual N-Channel, Digital FET
General Description
These dual N-Channel logic level enhancement mode
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This
very high density process is especially tailored to
minimize on-state resistance. This device has been
designed especially for low voltage applications as a
replacement for bipolar digital transistors and small
signal MOSFETs.
Features
25 V, 0.50 A continuous, 1.5 A peak.
R
DS(ON)
= 0.45
@ V
GS
= 4.5 V,
R
DS(ON)
=0.60
@ V
GS
= 2.7 V.
Very low level gate drive requirements allowing direct
operation in 3 V circuits (V
GS(th)
< 1.5 V).
Gate-Source Zener for ESD ruggedness
(>6kV Human Body Model).
Compact industry standard SC70-6 surface
mount package.
SC70-6
SOT-23
SuperSOT
TM
-6
SuperSOT
TM
-8
SO-8
SOT-223
G2
D1
S2
1 or 4
*
6 or 3
.33
2 or 5
5 or 2
SC70-6
S1
G1
D2
3 or 6
4 or 1
*
*
The pinouts are symmetrical; pin 1 and 4 are interchangeable.
Units inside the carrier can be of either orientation and will not affect the functionality of the device.
Absolute Maximum Ratings
Symbol
Parameter
T
A
= 25°C unless otherwise noted
FDG6313N
Units
V
DSS
V
GSS
I
D
P
D
T
J
,T
STG
ESD
Drain-Source Voltage
Gate-Source Voltage
Drain/Output Current
- Continuous
- Pulsed
Maximum Power Dissipation
(Note 1)
25
- 0.5 to +8
V
V
A
0.5
1.5
0.3
-55 to 150
6.0
W
°C
kV
Operating and Storage Temperature Range
Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100 pF / 1500
)
Thermal Resistance, Junction-to-Ambient
THERMAL CHARACTERISTICS
R
θJA
415
°C/W
FDG6313N Rev.A