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HCPL-2611WV 参数 Datasheet PDF下载

HCPL-2611WV图片预览
型号: HCPL-2611WV
PDF下载: 下载PDF文件 查看货源
内容描述: 高速10 Mbit / s的逻辑门光电耦合器 [High Speed-10 MBit/s Logic Gate Optocouplers]
分类和应用: 光电输出元件
文件页数/大小: 12 页 / 598 K
品牌: FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
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Single-Channel: 6N137, HCPL-2601, HCPL-2611 Dual-Channel: HCPL-2630, HCPL-2631 High Speed-10 MBit/s Logic Gate Optocouplers
Transfer Characteristics
(T
A
= -40 to +85°C Unless otherwise specified)
DC Characteristics
High Level Output Current
Low Level Output Current
Input Threshold Current
Test Conditions Symbol
(V
CC
= 5.5 V, V
O
= 5.5 V)
(I
F
= 250 µA, V
E
= 2.0 V) (Note 2)
(V
CC
= 5.5 V, I
F
= 5 mA)
(V
E
= 2.0 V, I
CL
= 13 mA) (Note 2)
(V
CC
= 5.5 V, V
O
= 0.6 V,
V
E
= 2.0 V, I
OL
= 13 mA)
I
OH
V
OL
I
FT
Min
Typ**
Max
100
Unit
µA
V
mA
.35
3
0.6
5
Isolation Characteristics
(T
A
= -40°C to +85°C Unless otherwise specified.)
Characteristics
Input-Output
Insulation Leakage
Current
Withstand Insulation Test Voltage
Test Conditions Symbol
(Relative humidity = 45%)
(T
A
= 25°C, t = 5 s)
(V
I-O
= 3000 VDC)
(Note 12)
(RH < 50%, T
A
= 25°C)
(I
I-O
2 µA)
(Note 12) ( t = 1 min.)
(V
I-O
= 500 V) (Note 12)
(f = 1 MHz) (Note 12)
I
I-O
Min
Typ**
Max
1.0*
Unit
µA
V
ISO
2500
V
RMS
Resistance (Input to Output)
Capacitance (Input to Output)
** All Typicals at V
CC
= 5V, T
A
= 25°C
R
I-O
C
I-O
10
12
0.6
pF
NOTES
1. The V
CC
supply to each optoisolator must be bypassed by a 0.1µF capacitor or larger. This can be either a ceramic or solid
tantalum capacitor with good high frequency characteristic and should be connected as close as possible to the package V
CC
and
GND pins of each device.
2. Each channel.
3. Enable Input - No pull up resistor required as the device has an internal pull up resistor.
4. t
PLH
-Propagation delay is measured from the 3.75 mA level on the HIGH to LOW transition of the input current pulse to the 1.5 V
level on the LOW to HIGH transition of the output voltage pulse.
5. t
PHL
-Propagation delay is measured from the 3.75 mA level on the LOW to HIGH transition of the input current pulse to the 1.5 V
level on the HIGH to LOW transition of the output voltage pulse.
6. t
r
-Rise time is measured from the 90% to the 10% levels on the LOW to HIGH transition of the output pulse.
7. t
f
-Fall time is measured from the 10% to the 90% levels on the HIGH to LOW transition of the output pulse.
8. t
ELH
-Enable input propagation delay is measured from the 1.5 V level on the HIGH to LOW transition of the input voltage pulse to
the 1.5 V level on the LOW to HIGH transition of the output voltage pulse.
9. t
EHL
-Enable input propagation delay is measured from the 1.5 V level on the LOW to HIGH transition of the input voltage pulse to
the 1.5 V level on the HIGH to LOW transition of the output voltage pulse.
10. CM
H
-The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the high state (i.e., V
OUT
> 2.0 V). Measured in volts per microsecond (V/µs).
11. CM
L
-The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the low output state (i.e.,
V
OUT
< 0.8 V). Measured in volts per microsecond (V/µs).
12. Device considered a two-terminal device: Pins 1,2,3 and 4 shorted together, and Pins 5,6,7 and 8 shorted together.
4
Single-Channel: 6N137, HCPL-2601, HCPL-2611 Dual-Channel: HCPL-2630, HCPL-2631 Rev. 1.0.5
www.fairchildsemi.com