KA7500C — SMPS Controller
Physical Dimensions
10.10
9.70
9.08
8.68
16
9
A
B
0.65
6.00
B
4.15
3.75
B
#1
8
1.27
0.51
0.36
0.20
TOP VIEW
C B A
1.75
#1
1.27
5.60
(0.30)
LAND PATTERN RECOMMENDATION
1.80 MAX
1.65
1.45
c
0.05 MIN
SEE DETAIL A
(R0.20)
0.303
0.153
B
SIDE VIEW
0.10 MAX C
END VIEW
NOTES:
A) THIS DRAWING GOMPLIES WITH JEDEC MS-012
EXCEPT AS NOTED.
B) THIS DEMENSION IS OUTSIDE THE JEDEC MS-012 VALUE.
C) ALL DIMENSIONS ARE IN MILLIMETERS.
D) DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,
AND TIE BAR EXTRUSIONS.
E) LANDPATTERN STANDARD: SOIC127P600X175-16AM.
F) DRAWING FILE NAME AND REVISION : M16EREV1
GAGE
PLANE
8¡Æ
(R0.10)
0.36
SEATING
PLANE
DETAIL A
0.90
0.50
Figure 3. 16-Lead Small Outline Package (SOP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2003 Fairchild Semiconductor Corporation
KA7500C • Rev. 1.0.2
www.fairchildsemi.com
6
FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
