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MM74HC151SJ 参数 Datasheet PDF下载

MM74HC151SJ图片预览
型号: MM74HC151SJ
PDF下载: 下载PDF文件 查看货源
内容描述: 8通道数字多路复用器 [8-Channel Digital Multiplexer]
分类和应用: 解复用器逻辑集成电路光电二极管
文件页数/大小: 7 页 / 74 K
品牌: FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
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MM74HC151 8-Channel Digital Multiplexer
September 1983
Revised February 1999
MM74HC151
8-Channel Digital Multiplexer
General Description
The MM74HC151 high speed Digital multiplexer utilizes
advanced silicon-gate CMOS technology. Along with the
high noise immunity and low power dissipation of standard
CMOS integrated circuits, it possesses the ability to drive
10 LS-TTL loads. The MM74HC151 selects one of the 8
data sources, depending on the address presented on the
A, B, and C inputs. It features both true (Y) and comple-
ment (W) outputs. The STROBE input must be at a low
logic level to enable this multiplexer. A high logic level at
the STROBE forces the W output HIGH and the Y output
LOW.
The 74HC logic family is functionally as well as pin-out
compatible with the standard 74LS logic family. All inputs
are protected from damage due to static discharge by inter-
nal diode clamps to V
CC
and ground.
Features
s
Typical propagation delay data select to output Y: 26 ns
s
Wide operating supply voltage range: 2–6V
s
Low input current: 1
µA
maximum
s
Low quiescent supply current: 80
µA
maximum (74HC)
s
High output drive current: 4 mA minimum
Ordering Code:
Order Number
MM74HC151M
MM74HC151SJ
MM74HC151MTC
MM74HC151N
Package Number
M16A
M16D
MTC16
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Truth Table
Inputs
Select
C
X
L
L
L
L
H
H
H
H
B
X
L
L
H
H
L
L
H
H
A
X
L
H
L
H
L
H
L
H
Strobe
S
H
L
L
L
L
L
L
L
L
Y
L
D0
D1
D2
D3
D4
D5
D6
D7
W
H
D0
D1
D2
D3
D4
D5
D6
D7
Outputs
Top View
H
=
HIGH Level, L
=
LOW Level, X
=
Don't Care
D0, D1...D7
=
the level of the respective D input
© 1999 Fairchild Semiconductor Corporation
DS005313.prf
www.fairchildsemi.com