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MM74HC393SJ 参数 Datasheet PDF下载

MM74HC393SJ图片预览
型号: MM74HC393SJ
PDF下载: 下载PDF文件 查看货源
内容描述: 双4位二进制计数器 [Dual 4-Bit Binary Counter]
分类和应用: 计数器触发器逻辑集成电路光电二极管
文件页数/大小: 8 页 / 90 K
品牌: FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
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MM74HC393
AC Electrical Characteristics
V
CC
=
5V, T
A
=
25
°
C, C
L
=
15 pF, t
r
=
t
f
=
6 ns
Symbol
f
MAX
t
PHL
, t
PLH
t
PHL
, t
PLH
t
PHL
, t
PLH
t
PHL
, t
PLH
t
PHL
t
REM
t
W
Parameter
Maximum Operating Frequency
Maximum Propagation Delay, Clock A to Q
A
Maximum Propagation Delay, Clock A to Q
B
Maximum Propagation Delay, Clock A to Q
C
Maximum Propagation Delay, Clock A to Q
D
Maximum Propagation Delay, Clear to any
Q
Minimum Removal Time
Minimum Pulse Width Clear or Clock
Conditions
Typ
50
13
19
23
27
15
−2
10
Guaranteed
Limit
30
20
35
42
50
28
5
16
Units
MHz
ns
ns
ns
ns
ns
ns
ns
AC Electrical Characteristics
C
L
=
50 pF, t
r
=
t
f
=
6 ns (unless otherwise specified)
Symbol
f
MAX
Parameter
Maximum Operating
Frequency
t
PHL
, t
PLH
Maximum Propagation
Delay Clock A to Q
A
t
PHL
, t
PLH
Maximum Propagation
Delay Clock A to Q
B
t
PHL
, t
PLH
Maximum Propagation
Delay Clock A to Q
C
t
PHL
, t
PLH
Maximum Propagation Delay
Clock to Q
D
t
PHL
Maximum Propagation
Delay Clear to any Q
t
REM
Minimum Clear
Removal Time
t
W
Minimum Pulse Width
Clear or Clock
t
THL
, t
TLH
Maximum Output
Rise and Fall Time
t
r
, t
f
Maximum Input
Rise and Fall Time
C
PD
C
IN
Power Dissipation
Capacitance (Note 5)
Maximum Input Capacitance
2
Conditions
V
CC
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
T
A
=
25°C
Typ
5
27
31
45
15
13
68
23
20
90
30
26
100
35
30
54
18
15
120
24
21
190
38
32
240
48
41
290
58
50
165
33
28
25
5
5
30
10
9
30
8
7
80
16
14
75
15
13
1000
500
400
T
A
= −40
to 85°C T
A
= −55
to 125°C
Guaranteed Limits
4
21
24
150
30
26
240
47
40
300
60
51
360
72
62
210
41
35
25
5
5
100
20
18
95
19
16
1000
500
400
3
18
20
180
35
31
285
57
48
360
72
61
430
87
75
250
49
42
25
5
5
120
24
20
110
22
19
1000
500
400
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
(per counter)
42
5
10
10
10
pF
Note 5:
C
PD
determines the no load dynamic power consumption, P
D
=
C
PD
V
CC
f
+
I
CC
V
CC
, and the no load dynamic current consumption,
I
S
=
C
PD
V
CC
f
+
I
CC
.
3
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