March 1996
NDC7001C
Dual N & P-Channel Enhancement Mode Field Effect Transistor
General Description
These dual N and P-channel enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process has been designed to minimize on-state resistance,
provide rugged and reliable performance and fast switching.
These devices is particularly suited for low voltage, low
current, switching, and power supply applications.
Features
N-Channel 0.51A, 50V, R
DS(ON)
= 2
Ω
@ V
GS
=10V
P-Channel -0.34A, -50V. R
DS(ON)
= 5
Ω
@ V
GS
=-10V.
High density cell design for low R
DS(ON)
.
Proprietary SuperSOT
TM
-6 package design using copper
lead frame for superior thermal and electrical capabilities.
High saturation current.
____________________________________________________________________________________________
4
3
5
2
6
SuperSOT
TM
-6
1
Absolute Maximum Ratings
Symbol
V
DSS
V
GSS
I
D
Parameter
Drain-Source Voltage
T
A
= 25°C unless otherwise noted
N-Channel
50
20
(Note 1a)
P-Channel
-50
-20
-0.34
-1
0.96
0.9
0.7
-55 to 150
Units
V
V
A
Gate-Source Voltage - Continuous
Drain Current - Continuous
- Pulsed
0.51
1.5
P
D
Maximum Power Dissipation
(Note 1a)
(Note 1b)
(Note 1c)
W
T
J
,T
STG
Operating and Storage Temperature Range
°C
THERMAL CHARACTERISTICS
R
θ
JA
R
θ
JC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
130
60
°C/W
°C/W
© 1997 Fairchild Semiconductor Corporation
NDC7001C.SAM
FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
