September 1997
NDP6020P / NDB6020P
P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
These logic level P-Channel enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process has been especially tailored to minimize on-state
resistance, provide superior switching performance, and
withstand high energy pulses in the avalanche and
commutation modes. These devices are particularly suited for
low voltage applications such as automotive, DC/DC
converters, PWM motor controls, and other battery powered
circuits where fast switching, low in-line power loss, and
resistance to transients are needed.
Features
-24 A, -20 V. R
DS(ON)
= 0.05
Ω
@ V
GS
= -4.5 V.
R
DS(ON)
= 0.07
Ω
@ V
GS
= -2.7 V.
R
DS(ON)
= 0.075
Ω
@ V
GS
= -2.5 V.
Critical DC electrical parameters specified at elevated
temperature.
Rugged internal source-drain diode can eliminate the need
for an external Zener diode transient suppressor.
175°C maximum junction temperature rating.
High density cell design for extremely low R
DS(ON)
.
TO-220 and TO-263 (D
2
PAK) package for both through
hole and surface mount applications.
________________________________________________________________________________
S
G
D
Absolute Maximum Ratings
Symbol
V
DSS
V
GSS
I
D
Parameter
Drain-Source Voltage
T
C
= 25°C unless otherwise noted
NDP6020P
-20
±8
-24
-70
60
0.4
-65 to 175
NDB6020P
Units
V
V
A
Gate-Source Voltage - Continuous
Drain Current
- Continuous
- Pulsed
P
D
Total Power Dissipation @ T
C
= 25°C
Derate above 25°C
W
W/°C
°C
T
J
,T
STG
Operating and Storage Temperature Range
© 1997 Fairchild Semiconductor Corporation
NDP6020P Rev.C1
FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
