April 1996
NDP6060L / NDB6060L
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
These logic level N-Channel enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This
very high density process has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulses in the
avalanche and commutation modes. These devices are
particularly suited for low voltage applications such as
automotive, DC/DC converters, PWM motor controls,
and other battery powered circuits where fast switching,
low in-line power loss, and resistance to transients are
needed.
Features
48A, 60V. R
DS(ON)
= 0.025
Ω
@ V
GS
= 5V.
Low drive requirements allowing operation directly from logic
drivers. V
GS(TH)
< 2.0V.
Critical DC electrical parameters specified at elevated
temperature.
Rugged internal source-drain diode can eliminate the need
for an external Zener diode transient suppressor.
175°C maximum junction temperature rating.
High density cell design for extremely low R
DS(ON)
.
TO-220 and TO-263 (D
2
PAK) package for both through hole
and surface mount applications.
________________________________________________________________________________
D
G
S
Absolute Maximum Ratings
Symbol
V
DSS
V
DGR
V
GSS
I
D
Parameter
Drain-Source Voltage
T
C
= 25°C unless otherwise noted
NDP6060L
60
60
± 16
± 25
48
144
100
0.67
-65 to 175
275
NDB6060L
Units
V
V
V
Drain-Gate Voltage (R
GS
< 1 M
Ω
)
Gate-Source Voltage - Continuous
- Nonrepetitive (t
P
< 50 µs)
Drain Current
- Continuous
- Pulsed
A
P
D
Total Power Dissipation @ T
C
= 25°C
Derate above 25°C
W
W/°C
°C
°C
T
J
,T
STG
T
L
Operating and Storage Temperature
Maximum lead temperature for soldering
purposes, 1/8" from case for 5 seconds
© 1997 Fairchild Semiconductor Corporation
NDP6060L Rev. D / NDB6060L Rev. E
FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
