June 1997
NDS336P
P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
SuperSOT
TM
-3 P-Channel logic level enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very high
density process is especially tailored to minimize on-state
resistance. These devices are particularly suited for low voltage
applications such as notebook computer power management,
portable electronics, and other battery powered circuits where
fast high-side switching, and low in-line power loss are needed
in a very small outline surface mount package.
Features
-1.2 A, -20 V, R
DS(ON)
= 0.27
Ω
@ V
GS
= -2.7 V
R
DS(ON)
= 0.2
Ω
@ V
GS
= -4.5 V.
Very low level gate drive requirements allowing direct
operation in 3V circuits. V
GS(th)
< 1.0V.
Proprietary package design using copper lead frame for
superior thermal and electrical capabilities.
High density cell design for extremely low R
DS(ON)
.
Exceptional on-resistance and maximum DC current
capability.
Compact industry standard SOT-23 surface
package.
Mount
________________________________________________________________________________
D
G
S
Absolute Maximum Ratings
Symbol
V
DSS
V
GSS
I
D
P
D
T
J
,T
STG
Parameter
Drain-Source Voltage
T
A
= 25°C unless otherwise noted
NDS336P
-20
±8
(Note 1a)
Units
V
V
A
Gate-Source Voltage - Continuous
Maximum Drain Current - Continuous
- Pulsed
Maximum Power Dissipation
(Note 1a)
(Note 1b)
-1.2
-10
0.5
0.46
-55 to 150
W
Operating and Storage Temperature Range
°C
THERMAL CHARACTERISTICS
R
θJA
R
θJC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
250
75
°C/W
°C/W
© 1997 Fairchild Semiconductor Corporation
NDS336P Rev. E
FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
