CMP1617BAx-E
CMOS LPRAM
PAGE WRITE CYCLE (Address controlled, /ZZ=VIH)
tMRC
tPC
tPC
tPC
tPC
tPC
tPC
tPC
tWC
A0~A3
A4~A20
/CS
/UB, /LB
/WE
tAS(3)
tDH
Data Valid
tOW
tDH tDW
tDH tDW tDH
tDH
Data Valid Data Valid Data Valid
tDW
tDW
tDW tDH
tDH
tDH tDW
tDW
tDW
Data in
High-Z
High-Z
Data Valid
Data Valid
Data Valid
Data Valid
tWHZ
Data Undefined
Data Out
1. A write occurs during the overlap (tWP) of low /CS and /WE. A write begins when /CS goes low and /WE goes low with
asserting /UB or /LB for single byte operation or simultaneously asserting /UB and /LB for double byte operation. A write
ends at the earliest transition when /CS goes high and /WE goes high. The tWP is measured from the beginning of write to
the end of write.
2. tCW is measured from the /CS going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high.
5. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 40us.
Revision 0.5
Jul. 2006
9
FIDELIX [ FIDELIX ]
