CMS3232LAx-75xx
Pin Description
Symbol
CLK
Type
Input
Description
Clock : CLK is driven by the system clock. All SDRAM input signals are sampled on the positive
edge of CLK. CLK also increments the internal burst counter and controls the output registers.
Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CLK signal. Deactivating the
clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation(all banks idle),
ACTIVE POWER-DOWN(row active in any bank) or CLOCK SUSPEND operation(burst/access
in progress). CKE is synchronous except after the device enters power-down and self refresh
modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers,
including CLK, are disabled during power-down and self refresh modes, providing low standby
power. CKE may be tied HIGH.
Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the command
decoder. All commands are masked when /CS is registered HIGH. /CS provides for external
bank selection on systems with multiple banks. /CS is considered part of the command code.
Command Inputs : /CAS, /RAS, and /WE (along with /CS) define the command being entered.
Input/Output Mask: DQM is sampled HIGH and is an input mask signal for write accesses
and an output enable signal for read accesses. Input data is masked during a WRITE cycle. The
output buffers are placed in a High-Z state (two-clock latency) when during a READ cycle.
DQM0 corresponds to DQ0 – DQ7, DQM1 corresponds to DQ8–DQ15,
DQM2 corresponds to DQ16–DQ23, AND DQM3 corresponds to DQ24–DQ31.
Bank Address Input(s): BS define to which bank the ACTIVE, READ, WRITE or
PRECHARGE command is being applied. These pins also provide the op-code during a LOAD
MODE REGISTER command.
Address Inputs: A0–A10 are sampled during the ACTIVE command (row-address A0–A10)
and READ/WRITE command (column-address A0–A7; with A10 defining auto precharge) to
select one location out of the memory array in the respective bank. A10 is sampled during a
PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank
selected by BS (A10 LOW). The address inputs also provide the op-code during a LOAD
MODE REGISTER command.
Data Input/Output : Data bus
No Connect
DQ Power: Provide isolated power to DQs for improved noise immunity.
DQ Ground: Provide isolated ground to DQs for improved noise immunity.
Power Supply: Voltage dependent on option.
Ground.
CKE
Input
/CS
Input
/CAS, /RAS, /WE
Input
DQM0 ~ DQM3
Input
BS
Input
A0-A10
Input
DQ
NC
V
DDQ
V
SSQ
V
DD
V
SS
I/O
-
Supply
Supply
Supply
Supply
Rev0.2, Jan. 2007
FIDELIX [ FIDELIX ]
