FMP1617DAx
Document Title
1M x 16 bit Super Low Power and Low Voltage Full CMOS RAM
CMOS LPRAM
Revision History
Revision
No.
0.0
Initial Draft
Revised Load Condition
Revised I/O power (1.7V to VCC
2.7V to VCC)
Revised VIH (VCC-0.4
0.8VCCQ)
Revised VIL (0.4
0.2VCCQ)
Revised ISB1 (110uA
100uA)
Revised ISB0c (110uA
100uA)
Revised ISB0b (100uA
80uA)
Revised ISB0a (90uA
70uA)
Correct typo in Array Refresh Area of Mode Register Set
Removed Page Write Operation
History
Draft date
Dec,08
th
, 2008
Remark
Preliminary
0.1
Jul. 3
rd
, 2009
Preliminary
0.2
Nov. 25
th
, 2009
Preliminary
0.3
0.4
Feb. 3
rd
, 2010
Jul. 21
st
, 2010
Preliminary
Final
1
Revision 0.4
Jul. 2010