FMP1617CAx
CMOS LPRAM
WRITE CYCLE (1) (/WE controlled, /ZZ=VIH)
tWC
Address
tCW(2)
tWR(4)
/CS
tAW
tBW
/UB, /LB
/WE
tWP(1)
tAS(3)
High-Z
tDW
Data Valid
tDH
Data in
High-Z
tWHZ
tOW
Data Out
Data Undefined
WRITE CYCLE (2) (/CS controlled, /ZZ=/WE=VIH)
tWC
Address
tWR(4)
tAS(3)
tCW(2)
/CS
tAW
tBW
/UB, /LB
/WE
tWP(1)
tDW
Data Valid
tDH
Data in
Data Out
High-Z
High-Z
WRITE CYCLE (3) (/UB, /LB controlled, /ZZ=VIH)
tWC
Address
tWR(4)
tCW(2)
tAW
/CS
tBW
/UB, /LB
tAS(3)
tWP(1)
/WE
tDW
Data Valid
tDH
Data in
Data Out
High-Z
High-Z
1. A write occurs during the overlap (tWP) of low /CS and /WE. A write begins when /CS goes low and /WE goes low with
asserting /UB or /LB for single byte operation or simultaneously asserting /UB and /LB for double byte operation. A write
ends at the earliest transition when /CS goes high and WE goes high. The tWP is measured from the beginning of write to
the end of write.
2. tCW is measured from the /CS going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high.
5. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us.
Revision 0.1
Jun. 2006
8
FIDELIX [ FIDELIX ]
