FMP1617CAx
WRITE CYCLE (1)
Address
tCW(2)
CMOS LPRAM
tWC
(/WE controlled, /ZZ=V
IH
)
/CS
tAW
tWR(4)
/UB, /LB
/WE
tAS(3)
tBW
tWP(1)
tDW
tDH
High-Z
tOW
Data in
Data Out
High-Z
tWHZ
Data Valid
Data Undefined
WRITE CYCLE (2)
Address
(/CS controlled, /ZZ=/WE=V
IH
)
tWC
tAS(3)
tCW(2)
tAW
tWR(4)
/CS
/UB, /LB
/WE
Data in
Data Out
High-Z
tBW
tWP(1)
tDW
tDH
Data Valid
High-Z
WRITE CYCLE (3)
Address
(/UB, /LB controlled, /ZZ=V
IH
)
tWC
tCW(2)
tWR(4)
/CS
tAW
/UB, /LB
tAS(3)
tBW
tWP(1)
/WE
Data in
Data Out
tDW
tDH
Data Valid
High-Z
High-Z
1. A write occurs during the overlap (tWP) of low /CS and /WE. A write begins when /CS goes low and /WE goes low with
asserting /UB or /LB for single byte operation or simultaneously asserting /UB and /LB for double byte operation. A write
ends at the earliest transition when /CS goes high and WE goes high. The tWP is measured from the beginning of write to
the end of write.
2. tCW is measured from the /CS going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high.
5. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us.
8
Revision 0.1
Jun. 2006
FIDELIX [ FIDELIX ]
