FMP3217BA0(7)
CMOS LPRAM
READ CYCLE (1) (Address controlled,/CS1=/OE=VIL, CS2=/WE=VIH, /UB or/and /LB=VIL)
tRC
Address
tAA
tOH
Data Out
Previous Data Valid
Data Valid
READ CYCLE (2) (CS2=/WE=VIH)
tRC
Address
tOH
tAA
tCO
/CS1
CS2
tHZ
tBA
/UB, /LB
/OE
tBHZ
tOE
tOLZ
tBLZ
tOHZ
tLZ
High-Z
Data Out
Data Valid
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced
to output voltage levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device
to device interconnection.
3. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us.
PAGE READ CYCLE (CS2=/WE=VIH, 16 words access)
tMRC
tPC
tPC
tPC
tPC
tPC
tPC
tPC
tRC
A0~A3
tAA
A4~A20
tOH
tCO
/CS1
CS2
tHZ
tBA
/UB, /LB
/OE
tBHZ
tOHZ
tOE
tOLZ
tPAA
tPAA
tPAA
tPAA
tPAA
tPAA
tPAA
tBLZ
tLZ
High-Z
Data Out
Data Valid Data Valid Data Valid Data Valid Data Valid Data Valid Data Valid Data Valid
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced
to output voltage levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device
to device interconnection.
3. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us.
4. In case page address skew is over 3ns, tPAA will be out of spec.
Revision 0.2
Feb. 2007
7
FIDELIX [ FIDELIX ]
