Freescale Semiconductor
Technical Data
DSP56311
Rev. 8, 2/2005
DSP56311
24-Bit Digital Signal Processor
3
16
6
6
Memory Expansion Area
Program
RAM
32 K
×
24 bits
or
31 K
×
24 bits
and
Instruction
Cache
1024
×
24 bits
PM_EB
SCI
Triple
Timer
HI08
ESSI
EFCOP
X Data
RAM
48 K
×
24 bits
Y Data
RAM
48 K
×
24 bits
PIO_EB
XM_EB
Address
Generation
Unit
Six Channel
DMA Unit
Bootstrap
ROM
YAB
XAB
PAB
DAB
YM_EB
Peripheral
Expansion Area
External
Address
Bus
Switch
External
Bus
Interface
and
I - Cache
Control
External
Data
Bus
Switch
Power
Management
JTAG
OnCE™
18
Address
24-Bit
DSP56300
Core
DDB
YDB
XDB
PDB
GDB
13
Control
The DSP56311 is intended
for applications requiring a
large amount of internal
memory, such as networking
and wireless infrastructure
applications. The onboard
EFCOP can accelerate
general filtering applications,
such as echo-cancellation
applications, correlation, and
general-purpose convolution-
based algorithms.
Internal
Data
Bus
Switch
24
Data
What’s New?
Rev. 8 includes the following
changes:
•
Adds lead-free packaging and
part numbers.
Clock
PLL
Generator
EXTAL
XTAL
RESET
PINIT/NMI
Program
Interrupt
Controller
Program
Decode
Controller
MODA/IRQA
MODB/IRQB
MODC/IRQC
MODD/IRQD
Program
Address
Generator
Data ALU
24
×
24 + 56
→
56-bit MAC
Two 56-bit Accumulators
56-bit Barrel Shifter
5
DE
PCAP
Figure 1.
DSP56311 Block Diagram
The Freescale DSP56311, a member of the DSP56300 DSP family, supports network applications with general filtering
operations. The Enhanced Filter Coprocessor (EFCOP) executes filter algorithms in parallel with core operations enhancing
signal quality with no impact on channel throughput or total channels supported. The result is increased overall performance.
Like the other DSP56300 family members, the DSP56311 uses a high-performance, single-clock-cycle-per- instruction engine
(DSP56000 code-compatible), a barrel shifter, 24-bit addressing, an instruction cache, and a direct memory access (DMA)
controller (see
The DSP56311 performs at up to 150 million multiply-accumulates per second (MMACS), attaining
up to 300 MMACS when the EFCOP is in use. It operates with an internal 150 MHz clock with a 1.8 volt core and
independent 3.3 volt input/output (I/O) power.
© Freescale Semiconductor, Inc., 1999, 2005. All rights reserved.
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