I/O Signals
3.7 I/O Signals
The ADC10 module shares its pins with general-purpose input/output (I/O) port pins. See
for
port location of these shared pins. The ADC10 on this MCU uses V
DD
and V
SS
as its supply and reference
pins. This MCU does not have an external trigger source.
3.7.1 ADC10 Analog Power Pin (V
DDA
)
The ADC10 analog portion uses V
DDA
as its power pin. In some packages, V
DDA
is connected internally
to V
DD
. If externally available, connect the V
DDA
pin to the same voltage potential as V
DD
. External filtering
may be necessary to ensure clean V
DDA
for good results.
NOTE
If externally available, route V
DDA
carefully for maximum noise immunity
and place bypass capacitors as near as possible to the package.
3.7.2 ADC10 Analog Ground Pin (V
SSA
)
The ADC10 analog portion uses V
SSA
as its ground pin. In some packages, V
SSA
is connected internally
to V
SS
. If externally available, connect the V
SSA
pin to the same voltage potential as V
SS
.
In cases where separate power supplies are used for analog and digital power, the ground connection
between these supplies should be at the V
SSA
pin. This should be the only ground connection between
these supplies if possible. The V
SSA
pin makes a good single point ground location.
3.7.3 ADC10 Voltage Reference High Pin (V
REFH
)
V
REFH
is the power supply for setting the high-reference voltage for the converter. In some packages,
V
REFH
is connected internally to V
DDA
. If externally available, V
REFH
may be connected to the same
potential as V
DDA
, or may be driven by an external source that is between the minimum V
DDA
spec and
the V
DDA
potential (V
REFH
must never exceed V
DDA
).
NOTE
Route
V
REFH
carefully for maximum noise immunity and place bypass
capacitors as near as possible to the package.
AC current in the form of current spikes required to supply charge to the capacitor array at each
successive approximation step is drawn through the V
REFH
and V
REFL
loop. The best external component
to meet this current demand is a 0.1
µF
capacitor with good high frequency characteristics. This capacitor
is connected between V
REFH
and V
REFL
and must be placed as close as possible to the package pins.
Resistance in the path is not recommended because the current will cause a voltage drop which could
result in conversion errors. Inductance in this path must be minimum (parasitic only).
3.7.4 ADC10 Voltage Reference Low Pin (V
REFL
)
V
REFL
is the power supply for setting the low-reference voltage for the converter. In some packages,
V
REFL
is connected internally to V
SSA
. If externally available, connect the V
REFL
pin to the same voltage
potential as V
SSA
. There will be a brief current associated with V
REFL
when the sampling capacitor is
charging. If externally available, connect the V
REFL
pin to the same potential as V
SSA
at the single point
ground location.
MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5
Freescale Semiconductor
53
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
