Opcode Map
Table 6-1. Instruction Set Summary (Sheet 6 of 6)
Operand
Address
Mode
Opcode
Source
Form
Operation
Description
PC
←
(PC) + 1; Push (PCL)
SP
←
(SP) – 1; Push (PCH)
SP
←
(SP) – 1; Push (X)
SP
←
(SP) – 1; Push (A)
SP
←
(SP) – 1; Push (CCR)
SP
←
(SP) – 1; I
←
1
PCH
←
Interrupt Vector High Byte
PCL
←
Interrupt Vector Low Byte
CCR
←
(A)
X
←
(A)
A
←
(CCR)
V H I N Z C
SWI
Software Interrupt
– – 1 – – – INH
83
TAP
TAX
TPA
TST
opr
TSTA
TSTX
TST
opr,X
TST ,X
TST
opr,SP
TSX
TXA
TXS
WAIT
A
C
CCR
dd
dd rr
DD
DIR
DIX+
ee ff
EXT
ff
H
H
hh ll
I
ii
IMD
IMM
INH
IX
IX+
IX+D
IX1
IX1+
IX2
M
N
Transfer A to CCR
Transfer A to X
Transfer CCR to A
↕ ↕ ↕ ↕ ↕ ↕
INH
– – – – – – INH
– – – – – – INH
DIR
INH
0 – –
↕ ↕
– INH
IX1
IX
SP1
– – – – – – INH
– – – – – – INH
– – – – – – INH
84
97
85
3D dd
4D
5D
6D ff
7D
9E6D ff
95
9F
94
Test for Negative or Zero
(A) – $00 or (X) – $00 or (M) – $00
Transfer SP to H:X
Transfer X to A
Transfer H:X to SP
Enable Interrupts; Wait for Interrupt
H:X
←
(SP) + 1
A
←
(X)
(SP)
←
(H:X) – 1
I bit
←
0; Inhibit CPU clocking
– – 0 – – – INH
8F
until interrupted
Accumulator
n
Any bit
Carry/borrow bit
opr
Operand (one or two bytes)
Condition code register
PC Program counter
Direct address of operand
PCH Program counter high byte
Direct address of operand and relative offset of branch instruction
PCL Program counter low byte
Direct to direct addressing mode
REL Relative addressing mode
Direct addressing mode
rel
Relative program counter offset byte
Direct to indexed with post increment addressing mode
rr
Relative program counter offset byte
High and low bytes of offset in indexed, 16-bit offset addressing
SP1 Stack pointer, 8-bit offset addressing mode
Extended addressing mode
SP2 Stack pointer 16-bit offset addressing mode
Offset byte in indexed, 8-bit offset addressing
SP Stack pointer
Half-carry bit
U
Undefined
Index register high byte
V
Overflow bit
High and low bytes of operand address in extended addressing
X
Index register low byte
Interrupt mask
Z
Zero bit
Immediate operand byte
&
Logical AND
Immediate source to direct destination addressing mode
|
Logical OR
Immediate addressing mode
⊕
Logical EXCLUSIVE OR
Inherent addressing mode
()
Contents of
Indexed, no offset addressing mode
–( ) Negation (two’s complement)
Indexed, no offset, post increment addressing mode
#
Immediate value
Indexed with post increment to direct addressing mode
«
Sign extend
Indexed, 8-bit offset addressing mode
←
Loaded with
Indexed, 8-bit offset, post increment addressing mode
?
If
Indexed, 16-bit offset addressing mode
:
Concatenated with
Memory location
↕
Set or cleared
Negative bit
—
Not affected
6.8 Opcode Map
See
MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5
Freescale Semiconductor
77
Cycles
9
2
1
1
3
1
1
3
2
4
2
1
2
1
Effect
on CCR
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
