I/O Signals
7.7 I/O Signals
The IRQ module does not share its pin with any module on this MCU.
7.7.1 IRQ Input Pins (IRQ)
The IRQ pin provides a maskable external interrupt source. The IRQ pin contains an internal pullup
device.
7.8 Registers
The IRQ status and control register (INTSCR) controls and monitors operation of the IRQ module. The
INTSCR:
• Shows the state of the IRQ flag
• Clears the IRQ latch
• Masks the IRQ interrupt request
• Controls triggering sensitivity of the IRQ interrupt pin
Bit 7
Read:
Write:
Reset:
0
0
= Unimplemented
0
0
0
0
6
0
5
0
4
0
3
IRQF
2
0
ACK
0
1
IMASK
0
Bit 0
MODE
0
Figure 7-3. IRQ Status and Control Register (INTSCR)
IRQF — IRQ Flag Bit
This read-only status bit is set when the IRQ interrupt is pending.
1 = IRQ interrupt pending
0 = IRQ interrupt not pending
ACK — IRQ Interrupt Request Acknowledge Bit
Writing a 1 to this write-only bit clears the IRQ latch. ACK always reads 0.
IMASK — IRQ Interrupt Mask Bit
Writing a 1 to this read/write bit disables the IRQ interrupt request.
1 = IRQ interrupt request disabled
0 = IRQ interrupt request enabled
MODE — IRQ Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the IRQ pin.
1 = IRQ interrupt request on falling edges and low levels
0 = IRQ interrupt request on falling edges only
MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5
Freescale Semiconductor
83
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
