KBI During Break Interrupts
8.6 KBI During Break Interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status
bits during the break state. See BFCR in the SIM section of this data sheet.
To allow software to clear status bits during a break interrupt, write a 1 to BCFE. If a status bit is cleared
during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a 0 to BCFE. With BCFE cleared (its default state),
software can read and write registers during the break state without affecting status bits. Some status bits
have a two-step read/write clearing procedure. If software does the first step on such a bit before the
break, the bit cannot change during the break state as long as BCFE is cleared. After the break, doing
the second step clears the status bit.
8.7 I/O Signals
The KBI module can share its pins with the general-purpose I/O pins. See
for the port pins that
are shared.
8.7.1 KBI Input Pins (KBI7:KBI0)
Each KBI pin is independently programmable as an external interrupt source. KBI pin polarity can be
controlled independently. Each KBI pin when enabled will automatically configure the appropriate
pullup/pulldown device based on polarity.
8.8 Registers
The following registers control and monitor operation of the KBI module:
•
•
•
KBSCR (keyboard interrupt status and control register)
KBIER (keyboard interrupt enable register)
KBIPR (keyboard interrupt polarity register)
8.8.1 Keyboard Status and Control Register (KBSCR)
Features of the KBSCR:
•
•
•
•
Flags keyboard interrupt requests
Acknowledges keyboard interrupt requests
Masks keyboard interrupt requests
Controls keyboard interrupt triggering sensitivity
MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5
Freescale Semiconductor
89
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
