Revision History
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The following revision history table summarizes changes contained in this document.
Revision
Number
1
2
Revision
Date
6/2006
9/2007
Description of Changes
Advance Information for alpha samples customers
Product Launch. Removed the 64-pin QFN package. Changed from standard to extended
mode for MSCAN registers in register summary. Corrected Block diagrams for SCI.
Updated the latest Temp Sensor information. Made FTSTMOD reserved. Updated device
to use the ADC 12-bit module. Revised the MCG module. Updated the CPU Instruction Set
table. Updated the TPM block module to version 3. Added the TPM block module version
2 as an appendix for devices using 3M05C (or earlier) mask sets. Heavily revised the
Electricals appendix.
Removed two tables that were inadvertently included in the MC9S08DZ60 version of the
book.
Sustaining update. Incorporated PS Issues # 2765, 3177, 3236, 3292, 3311, 3312, 3326,
3335, 3345, 3382, 2795, 3382 and 3386 PLL Jitter Spec update. Also, added internal
reference clock trim adjustment statement to Features page. Updated the TPM module to
the latest version. Adjusted values in Table A-13 Control Timing row 2 and in Table A-6 DC
Characteristics row 24 so that it references 5.0 V instead of 3.0 V.
3
4
10/2007
6/2008
© Freescale Semiconductor, Inc., 2007-2008. All rights reserved.
This product incorporates SuperFlash
®
Technology licensed from SST.
MC9S08DZ60 Series Data Sheet, Rev. 4
6
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
