Device Overview MC9S12P-Family
1.4
Block Diagram
VDDA
VSSA
VRH
VRL
AN[9:0]
Figure 1-1
shows a block diagram of the MC9S12P-Family devices
32K/64K/96K/128K bytes Flash
2K/4K/6K bytes RAM
4K bytes Data Flash
VDDR
VSS3
ATD
12-bit 10-channel
Analog-Digital Converter
PTAD
PTT
PTP (Wake-Up Int)
PTM
PTJ (Wake-up Int)
PTS
PAD[9:0]
PT0
PT1
PT2
PT3
PT4
PT5
PT6
PT7
PP0
PP1
PP2
PP3
PP4
PP5
PP7
PM0
PM1
PM2
PM3
PM4
PM5
Voltage Regulator
TIM
16-bit 8 channel
Timer
CPU12-V1
Debug Module
Single-wire Background 3 address breakpoints
Debug Module
1 data breakpoints
64 Byte Trace Buffer
IOC0
IOC1
IOC2
IOC3
IOC4
IOC5
IOC6
IOC7
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
BKGD
EXTAL
XTAL
VSSPLLL
RESET
TEST
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PWM
8-bit 6channel
Pulse Width Modulator
Amplitude Controlled
Low Power Pierce
Oscillator
PLL with Frequency
Modulation option
Reset Generation
and Test Entry
XIRQ
IRQ
Clock Monitor
COP Watchdog
Periodic Interrupt
Auton. Periodic Int.
Interrupt Module
CAN
msCAN 2.0B
SPI
Synchronous Serial IF
PTE
ECLK
RXCAN
TXCAN
MISO
SS
MOSI
SCK
ECLKX2
SCI
Asynchronous Serial IF
RXD
TXD
PA[7:0]
PB[7:0]
PTB
PTA
PS0
PS1
PS2
PS3
PJ0
PJ1
PJ2
3-5V IO Supply
VDDX1/VSSX1
VDDX2/VSSX2
PJ6
PJ7
Figure 1-1. MC9S12P-Family Block Diagram
S12P-Family Reference Manual, Rev. 1.13
24
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
