Peripheral operating requirements and behaviors
Table 37. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
(continued)
Num.
S12
Characteristic
Min.
45%
Max.
55%
Unit
MCLK period
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
S13
S14
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
30
3
—
—
ns
ns
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
S15
S16
S17
S18
S19
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid
I2S_RXD setup before I2S_RX_BCLK
—
0
63
—
—
—
72
ns
ns
ns
ns
ns
30
2
I2S_RXD hold after I2S_RX_BCLK
I2S_TX_FS input assertion to I2S_TXD output valid1
—
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
S11
S12
I2S_TX_BCLK/
S12
I2S_RX_BCLK (input)
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
S19
S14
I2S_TX_FS/
I2S_RX_FS (input)
S15
S16
S15
S16
I2S_TXD
I2S_RXD
S17
S18
Figure 22. I2S/SAI timing — slave modes
6.9 Human-machine interfaces (HMI)
6.9.1 TSI electrical specifications
Table 38. TSI electrical specifications
Symbol Description
VDDTSI Operating voltage
CELE Target electrode capacitance range
Min.
Typ.
Max.
Unit
Notes
1.71
—
3.6
V
1
20
500
pF
1
Table continues on the next page...
K10 Sub-Family Data Sheet, Rev. 4 5/2012.
52
Freescale Semiconductor, Inc.
FREESCALE [ Freescale ]
